display_release.map

MIPS的液晶显示原码,运行在ECLIPSE上,已通过测试.

Memory Configuration

Name             Origin             Length             Attributes
ram              0x0000000080000000 0x000000000001db00 xrw
flash            0x0000000081000000 0x000000000003f000 xr
sdram            0x0000000020000000 0x0000000002000000 xrw
flash0           0x0000000030000000 0x0000000000400000 xrw
flash1           0x0000000040000000 0x0000000002000000 xrw
sram             0x0000000050000000 0x0000000000200000 xrw
*default*        0x0000000000000000 0xffffffffffffffff

Linker script and memory map

                0x000000008001db00                __librom_sp = 0x8001db00

.com.vect.r     0x00000000a1000000      0x3fc
 *(.reset_vector)
 .reset_vector  0x00000000a1000000      0x3fc ../../lib/crt0.o
                0x00000000a10003ec                __warm_start
                0x00000000a1000000                reset_vector
                0x00000000a1000108                _start

.fake.vect.r    0x0000000081000000      0x3fc
                0x00000000810003fc                . = (. + SIZEOF (.com.vect.r))
 *fill*         0x0000000081000000      0x3fc 00
                0x0000000081000400                __com_rom_start = ((LOADADDR (.fake.vect.r) + SIZEOF (.fake.vect.r)) ALIGN 0x10)

.com.vect.e     0x0000000080000000        0xc load address 0x0000000081000400
                0x0000000080000000                __com_ram_start = .
 *(.except_vector)
 .except_vector
                0x0000000080000000        0xc ../../lib/crt0.o
                0x0000000080000000                hal_exception_handler

.com.vect.i     0x0000000080000180      0x584 load address 0x0000000081000580
 *(.other_vector)
 .other_vector  0x0000000080000180      0x584 ../../lib/crt0.o
                0x00000000800002ac                __default_interrupt_vsr
                0x0000000080000494                hal_default_isr
                0x00000000800001a4                __default_exception_vsr
                0x0000000080000180                other_vector
                0x00000000800004a0                __nmi_entry
                0x0000000080000684                hal_vsr_table
 *(.vsr_table)
 *(.text.ram)
                0x0000000080000704                __com_ram_end = .
                0x00000000a0000720                __com_bss_start = (ALIGN (0x20) | 0x20000000)

.com.bss        0x00000000a0000720        0x0
 *(.bss.usb)
                0x00000000a0000720                __com_bss_end = ALIGN (0x20)

.fake.bss       0x0000000080000704       0x1c
                0x0000000080000720                . = ALIGN (0x20)
 *fill*         0x0000000080000704       0x1c 00
                0x0000000080000720                . = (. + SIZEOF (.com.bss))
                0x0000000080000720                . = ALIGN (0x20)
                0x0000000081000b10                __com_rom_cont = ((LOADADDR (.com.vect.i) + SIZEOF (.com.vect.i)) ALIGN 0x10)

.com.vect       0x0000000081000b10       0xc0 load address 0x0000000081000b10
 *(.rom_vectors)
 .rom_vectors   0x0000000081000b10       0xc0 ../../lib/crt0.o
                0x0000000081000b80                __romcopy
                0x0000000081000b10                __zero_bss
                0x0000000081000ba8                __usip_init
 *(.text.rom)
                0x0000000081000bd0                . = ALIGN (0x10)

.com.stack      0x0000000080000720     0x1000
                0x0000000080000720                _sp_top = .
                0x0000000080001720                . = (. + 0x1000)
 *fill*         0x0000000080000720     0x1000 00
                0x0000000080001720                _sp = .

.text           0x0000000081000bd0      0x6bc
                0x0000000081000bd0        0x4 LONG 0x0
 *(.text)
 .text          0x0000000081000bd4      0x6b8 ././display1.o
                0x0000000081001100                display_hz
                0x0000000081000bd4                main
 *(.rodata*)
                0x0000000081001290                __rom_start = ((LOADADDR (.text) + SIZEOF (.text)) ALIGN 0x10)

.data           0x0000000080001720       0x20 load address 0x0000000081001290
                0x0000000080001720                __ram_start = .
 *(.data)
 .data          0x0000000080001720       0x20 ././display1.o
                0x0000000080001720                xin
 *(SORT(.dev*))
                0x0000000080009730                _gp = (ALIGN (0x10) + 0x7ff0)
 *(.sdata)
 *(.lit4 .lit8)
                0x0000000080001740                __ram_end = .

.sbss           0x0000000080001740        0x0
                0x0000000080001740                __bss_start = .
 *(.sbss .scommon)
 *(.bss COMMON)
                0x0000000080001740                . = ALIGN (0x20)
                0x0000000080001740                __bss_end = .

.rel.dyn
START GROUP
LOAD ././display1.o
LOAD ../../lib/crt0.o
LOAD ../../lib/libio/libio.a
LOAD ../../lib/libc/libc.a
END GROUP
OUTPUT(./display_release.elf elf32-tradlittlemips)

.reginfo        0x0000000000000000       0x18
 .reginfo       0x0000000000000000       0x18 ././display1.o

.pdr            0x0000000000000000      0x200
 .pdr           0x0000000000000000       0x80 ././display1.o
 .pdr           0x0000000000000080      0x180 ../../lib/crt0.o

.mdebug.abi32   0x0000000000000000        0x0

.debug_abbrev   0x0000000000000000      0x18f
 .debug_abbrev  0x0000000000000000      0x18f ././display1.o

.debug_info     0x0000000000000000      0x8d6
 .debug_info    0x0000000000000000      0x8d6 ././display1.o

.debug_line     0x0000000000000000      0x134
 .debug_line    0x0000000000000000      0x134 ././display1.o

.debug_frame    0x0000000000000000       0x70
 .debug_frame   0x0000000000000000       0x70 ././display1.o

.debug_pubnames
                0x0000000000000000       0x32
 .debug_pubnames
                0x0000000000000000       0x32 ././display1.o

.debug_aranges  0x0000000000000000       0x20
 .debug_aranges
                0x0000000000000000       0x20 ././display1.o

.debug_str      0x0000000000000000       0x4a
 .debug_str     0x0000000000000000       0x4a ././display1.o

.comment        0x0000000000000000       0x2b
 .comment       0x0000000000000000       0x2b ././display1.o