platform.h

au1200下的boot代码

#ifndef DB1200
#define DB1200
#endif
#define AU1200


// NAND
#define NAND_CE0			21			// gpio no.	
#define NAND_CE1			20			// gpio no.	

// SD
//#define SD0_INSERT		0
//#define SD0_WP			212

// IDE
#define IDE_RST			17			// gpio no.
#define IDE_BUF_EN			10			// gpio no.
#define IDE_PWR			19			// gpio no.

// LCD
#define LCD_BL_PWR			16			// gpio no.
#define LCD_PWR			15			// gpio no.
#define LCD_BL_PWR_ACTIVE		1			// 0:low 1:high
#define LCD_PWR_ACTIVE		1			// 0:low 1:high
#define _LCD_OUTPUT_
#define LCD_STATUS

// boot
#define AUTO_BOOT_SWITCH		208			// gpio no.
#define AUTO_BOOT_SWITCH_ACTIVE	1			// 0:low 1:high

/*
 * Frequency info
 */
#define CPU_FREQUENCY		(12000000 * 33)
#define CPU_SD			2

/*
 * DMA
 */
#define DBDMA_AC97_TX_CHAN	DSCR_CMD0_PSC0_TX 
#define DBDMA_AC97_RX_CHAN	DSCR_CMD0_PSC0_RX
#define DBDMA_I2S_TX_CHAN		DSCR_CMD0_PSC0_TX
#define DBDMA_I2S_RX_CHAN		DSCR_CMD0_PSC0_RX

/* SPI and SMB are muxed on the Db1200 board.
   Refer to board documentation.
 */
#define SPI_PSC_BASE		PSC1_PHYS_ADDR
#define SMBUS_PSC_BASE		PSC1_PHYS_ADDR

/* AC97 and I2S are muxed on the Db1200 board.
   Refer to board documentation.
 */
#define AC97_PSC_BASE		PSC0_PHYS_ADDR
#define I2S_PSC_BASE		PSC0_PHYS_ADDR

#define NOR_PHYS_ADDR		0x1E000000
#define BCSR_PHYS_ADDR		0x1C000000

#ifndef ASSEMBLER
static volatile unsigned short* bcsr = (volatile unsigned short*) KSEG1(BCSR_PHYS_ADDR);
#endif

/*
 * Register bit definitions for the BCSRs  */
#define BCSR_TV_OUT_EN		0x8000
#define BCSR_LCD_PWR		0x4000
#define BCSR_IDE_PWR		0x2000
#define BCSR_USB_HOST_PWR		0x1000
#define BCSR_AMP_EN			0x0800
#define BCSR_IDE_BUF_EN		0x0400
#define BCSR_FM_EN			0x0200
#define BCSR_PVI_RST		0x0080
#define BCSR_ETN_RST		0x0040
#define BCSR_CF_RST			0x0020
#define BCSR_IDE_RST		0x0010
#define BCSR_TV_OUT_RST		0x0008
#define BCSR_LCD_CTRL		0x0004

/* SMSC LAN91C111 */
#define AU1XXX_SMC91111_BASE		(0xA9000000)
#define AU1XXX_SMC91111_END		(0xA97FFFFF)
#define AU1XXX_SMC91111_MEM_SIZE	(AU1XXX_SMC91111_END - AU1XXX_SMC91111_BASE + 1)
// shared IRQs
#define AU1XXX_SMC91111_IRQ		AU1X00_EXTERNAL_INT

/* DC_IDE and DC_ETHERNET */
#define AU1XXX_ATA_BASE			(0xA8800000)
#define AU1XXX_ATA_END			(0xA8FFFFFF)
#define AU1XXX_ATA_MEM_SIZE		(AU1XXX_ATA_END - AU1XXX_ATA_BASE +1)

#define AU1XXX_ATA_REG_OFFSET		(5)
#define AU1XXX_SMC91111_OFFSET		(0x300)

#define IDE_PHYS_ADDR			0x18800000

//#define NAND_PHYS_ADDR   		0x1C000000

#define PCMCIA_MAX_SOCK			1
#define PCMCIA_NUM_SOCKS			(PCMCIA_MAX_SOCK+1)

#define SD_NUM_SLOTS			1

#define PCMCIA_PC_IRQ			7
#define PCMCIA_PC0_IRQ			PCMCIA_PC_IRQ
#define PCMCIA_PC1_IRQ			PCMCIA_PC_IRQ
#define PCMCIA_CARD_COUNT			2


#define FLASH_AMD_MIRRORBIT
#define FLASH_START_PHYS_ADDRESS	0x1C000000
#define FLASH_END_PHYS_ADDRESS		0x1FFFFFFF
#define FLASH_BLOCK_SIZE			0x00020000
#define FLASH_ALTERNATE_ADDR		0xBDC00000