crt0.lst

au1200下的boot代码

 525      00000000 
 525      00908440 
 526 05e0 01900240 	CP0(IWatchLo)
 526      0800E003 
 526      00000000 
 526      00000000 
 526      01908440 
 527 0600 00980240 	CP0(WatchHi)
 527      0800E003 
 527      00000000 
 527      00000000 
 527      00988440 
 528 0620 01980240 	CP0(IWatchHi)
 528      0800E003 
 528      00000000 
 528      00000000 
 528      01988440 
 529 0640 00B00240 	CP0(Scratch)
 529      0800E003 
 529      00000000 
 529      00000000 
 529      00B08440 
 530 0660 00B80240 	CP0(Debug)
 530      0800E003 
 530      00000000 
 530      00000000 
 530      00B88440 
 531 0680 00C00240 	CP0(DEPC)
 531      0800E003 
 531      00000000 
 531      00000000 
 531      00C08440 
 532 06a0 00C80240 	CP0(PerfCnt)
 532      0800E003 
 532      00000000 
 532      00000000 
 532      00C88440 
 533 06c0 01C80240 	CP0(PerfCtrl)
 533      0800E003 
 533      00000000 
 533      00000000 
 533      01C88440 
 534 06e0 00E00240 	CP0(DTag)
 534      0800E003 
GAS LISTING /tmp/ccZtg9Qb.s 			page 13


 534      00000000 
 534      00000000 
 534      00E08440 
 535 0700 01E00240 	CP0(DData)
 535      0800E003 
 535      00000000 
 535      00000000 
 535      01E08440 
 536 0720 00E80240 	CP0(ITag)
 536      0800E003 
 536      00000000 
 536      00000000 
 536      00E88440 
 537 0740 01E80240 	CP0(IData)
 537      0800E003 
 537      00000000 
 537      00000000 
 537      01E88440 
 538 0760 00F00240 	CP0(ErrorEPC)
 538      0800E003 
 538      00000000 
 538      00000000 
 538      00F08440 
 539 0780 00F80240 	CP0(DESave)
 539      0800E003 
 539      00000000 
 539      00000000 
 539      00F88440 
 540              	
 541              	########################################################################
 542              	
 543              	/*
 544              	 * Generic TLB Refill Exception Handler
 545              	 *
 546              	 * Support a two-level PTE scheme for 4KB pages where:
 547              	 *
 548              	 *     3322222222221111111111
 549              	 *     10987654321098765432109876543210
 550              	 * VA +--------------------------------+
 551              	 *    |                                |
 552              	 *    +--------------------------------+
 553              	 *
 554              	 * Bits 31..24 form an index into a 256-entry pointer array to the PTE
 555              	 * Bits 23..12 form an index into a 4096-entry PTE array
 556              	 *
 557              	 * Can only use K0 and K1.
 558              	 * This handler will be installed to 0x80000000, and is limited to X
 559              	 * insns in size else it spills into the next vector.
 560              	 * Assumes CP0_PageMask has been set to 4K (and left alone)
 561              	 * Can NOT use at explicitly or implicity in these insns
 562              	 */
 563              	
 564              		.global asmTlbRefillHandler
 565              		.extern L1PTE
 566              		.set noat
 567              	asmTlbRefillHandler:
 568 07a0 00001A3C 		la		k0,L1PTE
GAS LISTING /tmp/ccZtg9Qb.s 			page 14


 568      00005A27 
 569              		//mfc0	k0, CP0_Context # Context requires specific alignment
 570 07a8 00401B40 		mfc0	k1, CP0_BadVAddr
 571 07ac 02DE1B00 		srl		k1, k1, 24	/* 24 - (2 for 32-bit pointer) */
 572 07b0 80D81B00 		sll		k1, k1, 2
 573 07b4 21D05B03 		addu	k0, k0, k1
 574 07b8 00005A8F 		lw		k0, 0(k0)	/* pointer to PTE array */
 575 07bc 0F004013 		beq		k0, zero, noPTE
 575      00000000 
 576 07c4 00000000 		nop
 577 07c8 00401B40 		mfc0	k1, CP0_BadVAddr
 578 07cc 00DA1B00 		sll		k1, 8
 579 07d0 42DD1B00 		srl		k1, k1, 21	/* 8 + 13 - (2 for 32-bit PTE) - (1 for VPN/2) */
 580 07d4 C0D81B00 		sll		k1, k1, 3
 581 07d8 21D05B03 		addu	k0, k0, k1	/* point to PTE */
 582 07dc 00005B8F 		lw		k1, 0(k0)	/* EntryLo0 */
 583 07e0 00109B40 		mtc0	k1, CP0_EntryLo0
 584 07e4 04005B8F 		lw		k1, 4(k0)
 585 07e8 00189B40 		mtc0	k1, CP0_EntryLo1
 586 07ec 06000042 		tlbwr
 587 07f0 00000000 		nop
 588 07f4 18000042 		eret
 589 07f8 00000000 		nop
 590              	noPTE:	/* Will cause a TLB Invalid Exception */
 591 07fc 00108040 		mtc0	zero, CP0_EntryLo0
 592 0800 00188040 		mtc0	zero, CP0_EntryLo1
 593 0804 06000042 		tlbwr
 594 0808 00000000 		nop
 595 080c 18000042 		eret
 596 0810 00000000 		nop
 597              		.global asmTlbRefillHandlerEnd
 598              	asmTlbRefillHandlerEnd:
 599              		.set at
 600              	
 601              	
 602              	########################################################################
 603              	
 604              	/*
 605              	 * Generic IRQ Handler. It merely saves context on the STACK
 606              	 * C code will copy this to the interrupt exception vector
 607              	 * at 0x80000200. No other exception vectors after 0x0200, so
 608              	 * this code can be as large as it needs.
 609              	 */
 610              	
 611              	/* 29 gprs (no zero, k0 or k1), Hi, Lo, Status */
 612              	#define CONTEXT_SIZE	((29 + 1 + 1 + 1) * 4)
 613              	
 614              		.global asmIrqHandler
 615              		.extern cpuIrqHandler
 616              	asmIrqHandler:
 617              	
 618              	asmContextSave:
 619              		.set	noat
 620              	
 621              		# Compute stack frame size
 622 0814 80FFBA27 		addiu	k0,sp,-CONTEXT_SIZE
 623 0818 000041AF 		sw		$1,0(k0)
GAS LISTING /tmp/ccZtg9Qb.s 			page 15


 624 081c 040042AF 		sw		v0,4(k0)
 625 0820 080043AF 		sw		v1,8(k0)
 626 0824 0C0044AF 		sw		a0,12(k0)
 627 0828 100045AF 		sw		a1,16(k0)
 628 082c 140046AF 		sw		a2,20(k0)
 629 0830 180047AF 		sw		a3,24(k0)
 630 0834 1C0048AF 		sw		t0,28(k0)
 631 0838 200049AF 		sw		t1,32(k0)
 632 083c 24004AAF 		sw		t2,36(k0)
 633 0840 28004BAF 		sw		t3,40(k0)
 634 0844 2C004CAF 		sw		t4,44(k0)
 635 0848 30004DAF 		sw		t5,48(k0)
 636 084c 34004EAF 		sw		t6,52(k0)
 637 0850 38004FAF 		sw		t7,56(k0)
 638 0854 3C0050AF 		sw		s0,60(k0)
 639 0858 400051AF 		sw		s1,64(k0)
 640 085c 440052AF 		sw		s2,68(k0)
 641 0860 480053AF 		sw		s3,72(k0)
 642 0864 4C0054AF 		sw		s4,76(k0)
 643 0868 500055AF 		sw		s5,80(k0)
 644 086c 540056AF 		sw		s6,84(k0)
 645 0870 580057AF 		sw		s7,88(k0)
 646 0874 5C0058AF 		sw		t8,92(k0)
 647 0878 600059AF 		sw		t9,96(k0)
 648 087c 64005CAF 		sw		gp,100(k0)
 649 0880 68005DAF 		sw		sp,104(k0)
 650 0884 6C005EAF 		sw		fp,108(k0)
 651 0888 70005FAF 		sw		ra,112(k0)
 652 088c 10400000 		mfhi	t0
 653 0890 12480000 		mflo	t1
 654 0894 00601B40 		mfc0	k1,CP0_Status
 655 0898 00000000 		nop
 656 089c 740048AF 		sw		t0,116(k0)
 657 08a0 780049AF 		sw		t1,120(k0)
 658 08a4 7C005BAF 		sw		k1,124(k0)
 659              	
 660              		# Update stack pointer
 661 08a8 00005D27 		addiu	sp,k0,0
 662              	
 663              		# Invoke C interrupt handler, IRQs still disabled
 664              		# jal cannot be used because this code is linked to a different location than it executes
 665              		#     therefore it is possible to overrun the bounds of the 26-bit relative address used in the ja
 666 08ac 0000083C 		la		t0, cpuIrqHandler
 666      00000825 
 667 08b4 09F80001 		jalr	t0
 667      00000000 
 668 08bc 00000000 		nop
 669              	
 670              	asmContextRestore:
 671              	
 672              		# Update stack pointer
 673 08c0 0000BA27 		addiu	k0,sp,0
 674              	
 675 08c4 7400488F 		lw		t0,116(k0)
 676 08c8 7800498F 		lw		t1,120(k0)
 677 08cc 7C005B8F 		lw		k1,124(k0)
 678 08d0 11000001 		mthi	t0
GAS LISTING /tmp/ccZtg9Qb.s 			page 16


 679 08d4 13002001 		mtlo	t1
 680 08d8 0000418F 		lw		$1,0(k0)
 681 08dc 0400428F 		lw		v0,4(k0)
 682 08e0 0800438F 		lw		v1,8(k0)
 683 08e4 0C00448F 		lw		a0,12(k0)
 684 08e8 1000458F 		lw		a1,16(k0)
 685 08ec 1400468F 		lw		a2,20(k0)
 686 08f0 1800478F 		lw		a3,24(k0)
 687 08f4 1C00488F 		lw		t0,28(k0)
 688 08f8 2000498F 		lw		t1,32(k0)
 689 08fc 24004A8F 		lw		t2,36(k0)
 690 0900 28004B8F 		lw		t3,40(k0)
 691 0904 2C004C8F 		lw		t4,44(k0)
 692 0908 30004D8F 		lw		t5,48(k0)
 693 090c 34004E8F 		lw		t6,52(k0)
 694 0910 38004F8F 		lw		t7,56(k0)
 695 0914 3C00508F 		lw		s0,60(k0)
 696 0918 4000518F 		lw		s1,64(k0)
 697 091c 4400528F 		lw		s2,68(k0)
 698 0920 4800538F 		lw		s3,72(k0)
 699 0924 4C00548F 		lw		s4,76(k0)
 700 0928 5000558F 		lw		s5,80(k0)
 701 092c 5400568F 		lw		s6,84(k0)
 702 0930 5800578F 		lw		s7,88(k0)
 703 0934 5C00588F 		lw		t8,92(k0)
 704 0938 6000598F 		lw		t9,96(k0)
 705 093c 64005C8F 		lw		gp,100(k0)
 706 0940 68005D8F 		lw		sp,104(k0)
 707 0944 6C005E8F 		lw		fp,108(k0)
 708 0948 70005F8F 		lw		ra,112(k0)
 709 094c 00609B40 		mtc0	k1,CP0_Status
 710 0950 00000000 		nop
 711 0954 18000042 		eret
 712 0958 00000000 		nop
 713              	
 714              		.set	at
 715              	
 716              		.global asmIrqHandlerEnd
 717              	asmIrqHandlerEnd:
 718              	
 719              	#undef C0_Count
 720              	#define C0_Count	$9
 721              	
 722              	//
 723              	//	delay_count(int n)
 724              	//
 725              	//	delay n tics of the count register (not exact)
 726              	//
 727              		.globl	delay_count
 728              	delay_count:
 729 095c 00480840 		mfc0	t0,C0_Count		// get starting count value
 730              	del1:
 731 0960 0F000000 		sync
 732 0964 00480940 		mfc0	t1,C0_Count		// get current count
 733 0968 23482801 		subu	t1,t0			// subtract start count
 734 096c 23482401 		subu	t1,a0			// see if past n
 735 0970 FBFF2005 		bltz	t1,del1
GAS LISTING /tmp/ccZtg9Qb.s 			page 17


 735      00000000 
 736 0978 0800E003 		jr	ra
 736      00000000 
 737              	
 738              	#define C0_Config		$16
 739              	//
 740              	//	ulong	set_endian(ulong value)
 741              	//
 742              	//	sets the endianness register to value and returns the previous contents
 743              	//
 744              		.globl	set_endian
 745              	set_endian:
 746 0980 90B1053C 		la	a1,0xb1900038		// point to endianness reg
 746      3800A534 
 747 0988 0000A28C 		lw	v0,(a1)			// get previous value
 748 098c 0000A4AC 		sw	a0,(a1)			// set new value
 749 0990 00000000 		nop
 750 0994 00000000 		nop
 751 0998 00800340 		mfc0	v1,C0_Config		// trigger the change
 752 099c 00808340 		mtc0	v1,C0_Config
 753 09a0 0800E003 		jr	ra
 753      00000000 
 754              	
 755              	asm_move:
 756 09a8 0000888C 		lw	t0,(a0)
 757 09ac 0400898C 		lw	t1,4(a0)
 758 09b0 08008A8C 		lw	t2,8(a0)
 759 09b4 0C008B8C 		lw	t3,12(a0)
 760 09b8 10008C8C 		lw	t4,16(a0)
 761 09bc 14008D8C 		lw	t5,20(a0)
 762 09c0 18008E8C 		lw	t6,24(a0)
 763 09c4 1C008F8C 		lw	t7,28(a0)
 764 09c8 E0FFC620 		sub	a2,32
 765 09cc 0000A8AC 		sw	t0,(a1)
 766 09d0 0400A9AC 		sw	t1,4(a1)
 767 09d4 0800AAAC 		sw	t2,8(a1)
 768 09d8 0C00ABAC 		sw	t3,12(a1)
 769 09dc 1000ACAC 		sw	t4,16(a1)
 770 09e0 1400ADAC 		sw	t5,20(a1)
 771 09e4 1800AEAC 		sw	t6,24(a1)
 772 09e8 1C00AFAC 		sw	t7,28(a1)
 773 09ec 20008420 		add	a0,32
 774 09f0 2000A520 		add	a1,32
 775 09f4 ECFFC01C 		bgtz	a2,asm_move
 775      00000000 
 776 09fc 0800E003 		jr	ra
 776      00000000 
 776      00000000 
 776      00000000 
 776      00000000