📄 crt0.lst
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295 /* the layout of CSMASK and E happen to be the same in all controllers */ 296 computeCSsize: 297 0160 10000B3C li t3, (1<<20) /* mem_sdaddr[E] */ 298 0164 24502B01 and t2, t1, t3 299 0168 07004011 beq t2, zero, 1f 299 00000000 300 0170 00000000 nop 301 0174 804D0900 sll t1, 22 /* justify mem_sdaddr[CSMASK] */ 302 0178 FFFF0124 xor t1, 0xFFFFFFFF /* complement */ 302 26482101 303 0180 01002925 addiu t1, 1 /* size */ 304 0184 21104900 addu v0, t1 /* accumulate */ 305 1: 306 0188 0800E003 jr ra 306 00000000 307 0190 00000000 nop 308 309 .global sizeDRAM 310 sizeDRAM: 311 .set noreorder 312 0194 00000224 li v0, 0 313 0198 2118E003 move v1, ra GAS LISTING /tmp/ccZtg9Qb.s page 7 314 315 019c 00780840 mfc0 t0, CP0_PRId 316 01a0 00FF093C li t1, 0xFF000000 317 01a4 24400901 and t0, t1 318 01a8 02460800 srl t0, 24 319 01ac 04000924 li t1, 4 320 01b0 16000911 beq t0, t1, sizeAu1200 321 01b4 00000000 nop 322 01b8 03000924 li t1, 3 323 01bc 0A000911 beq t0, t1, sizeAu1550 324 01c0 00000000 nop 325 326 sizeAu1000: 327 sizeAu1500: 328 sizeAu1100: 329 01c4 00B4083C li t0, 0xB4000000 330 01c8 5800000C jal computeCSsize 331 01cc 0C00098D lw t1, 0x000C(t0) /* mem_sdaddr0 */ 332 01d0 5800000C jal computeCSsize 333 01d4 1000098D lw t1, 0x0010(t0) /* mem_sdaddr1 */ 334 01d8 5800000C jal computeCSsize 335 01dc 1400098D lw t1, 0x0014(t0) /* mem_sdaddr2 */ 336 01e0 11000010 b sizeDRAMdone 337 01e4 00000000 nop 338 339 sizeAu1550: 340 01e8 00B4083C li t0, 0xB4000000 341 01ec 5800000C jal computeCSsize 342 01f0 2008098D lw t1, 0x0820(t0) /* mem_sdaddr0 */ 343 01f4 5800000C jal computeCSsize 344 01f8 2808098D lw t1, 0x0828(t0) /* mem_sdaddr1 */ 345 01fc 5800000C jal computeCSsize 346 0200 3008098D lw t1, 0x0830(t0) /* mem_sdaddr2 */ 347 0204 08000010 b sizeDRAMdone 348 0208 00000000 nop 349 350 sizeAu1200: 351 020c 00B4083C li t0, 0xB4000000 352 0210 5800000C jal computeCSsize 353 0214 2008098D lw t1, 0x0820(t0) /* mem_sdaddr0 */ 354 0218 5800000C jal computeCSsize 355 021c 2808098D lw t1, 0x0828(t0) /* mem_sdaddr1 */ 356 0220 01000010 b sizeDRAMdone 357 0224 00000000 nop 358 359 sizeDRAMdone: 360 0228 21F86000 move ra, v1 361 022c 0800E003 jr ra 362 0230 00000000 nop 363 364 #.set reorder 365 366 367 ######################################################################## 368 369 /* 370 * Power savings Idle mode routine GAS LISTING /tmp/ccZtg9Qb.s page 8 371 */ 372 .global au1_wait 373 au1_wait: 374 0234 0000083C la t0,au1_wait # obtain address of au1_wait 374 00000825 375 023c 000014BD cache 0x14,0(t0) # fill icache with first 8 insns 376 0240 200014BD cache 0x14,32(t0) # fill icache with next 8 insns 377 0244 0F000000 sync # empty WB to prevent bus activity 378 0248 00000000 nop 379 024c 20000042 wait 0 380 0250 00000000 nop 381 0254 00000000 nop 382 0258 00000000 nop 383 025c 00000000 nop 384 0260 0800E003 j ra 385 0264 00000000 nop 386 387 ######################################################################## 388 389 /* 390 * Routine to initialize the data cache for streaming data. This 391 * routine accepts a base address to a buffer and configures the 392 * data cache for streaming accesses by locking Way 0 of each of 393 * the 128 data cache sets. 394 * 395 * a0 is buffer address, must be cache line aligned 396 */ 397 .global dcacheStreamInit 398 .set noreorder 399 dcacheStreamInit: 400 0268 80000824 li t0,128 # number of dcache sets 401 dcsiloop: 402 026c 000095BC cache 0x15,0(a0) # wb inv address if in cache 403 0270 000084CC pref 0x4,0(a0) # streaming prefetch into way 0 404 0274 00009DBC cache 0x1D,0(a0) # dcache fetch and lock 405 0278 FFFF0825 addiu t0,t0,-1 # decrement sets 406 027c FBFF0814 bne zero,t0,dcsiloop 407 0280 20008424 addiu a0,a0,32 # increment address by cacheline size 408 0284 0800E003 j ra 409 0288 00000000 nop 410 .set reorder 411 412 ######################################################################## 413 414 .global asmTlbInit 415 asmTlbInit: 416 028c 00000824 li t0, 0 # index value 417 0290 00000924 li t1, 0x00000000 # entryhi value 418 0294 20000A24 li t2, 32 # 32 entries 419 tlbl: 420 /* Probe TLB for matching EntryHi */ 421 0298 00508940 mtc0 t1, CP0_EntryHi 422 029c 08000042 tlbp 423 02a0 00000000 nop 424 425 /* Examine Index[P], 1=no matching entry */ 426 02a4 00000B40 mfc0 t3, CP0_Index GAS LISTING /tmp/ccZtg9Qb.s page 9 427 02a8 00800C3C li t4, 0x80000000 428 02ac 24588B01 and t3, t4, t3 429 02b0 01002925 addiu t1, t1, 1 # increment t1 (asid) 430 02b4 F8FF0B10 beq zero, t3, tlbl 430 00000000 431 02bc 00000000 nop 432 433 /* Initialize the TLB entry */ 434 02c0 00008840 mtc0 t0, CP0_Index 435 02c4 00108040 mtc0 zero, CP0_EntryLo0 436 02c8 00188040 mtc0 zero, CP0_EntryLo1 437 02cc 00288040 mtc0 zero, CP0_PageMask 438 02d0 02000042 tlbwi 439 440 /* Do it again */ 441 02d4 01000825 addiu t0, t0, 1 442 02d8 EFFF0A15 bne t0, t2, tlbl 442 00000000 443 02e0 00000000 nop 444 445 /* Establish Wired (and Random) */ 446 02e4 00308040 mtc0 zero, CP0_Wired 447 02e8 00000000 nop 448 02ec 0800E003 j ra 448 00000000 449 02f4 00000000 nop 450 451 452 // 453 // void tlbWrite(int index, TLBEntry *p); 454 // 455 // when index is -1 then a write random will be done. 456 // 457 .globl tlbWrite 458 tlbWrite: 459 02f8 0000A88C lw t0,(a1) 460 02fc 00108840 mtc0 t0,CP0_EntryLo0 461 0300 0400A88C lw t0,4(a1) 462 0304 00288840 mtc0 t0,CP0_PageMask 463 0308 0800A88C lw t0,8(a1) 464 030c 00188840 mtc0 t0,CP0_EntryLo1 465 0310 0C00A88C lw t0,12(a1) 466 0314 00508840 mtc0 t0,CP0_EntryHi 467 0318 08008004 bltz a0,tlbWrite1 # write random if index < 0 467 00000000 468 0320 00008440 mtc0 a0,CP0_Index # set index register 469 0324 02000042 tlbwi 470 0328 00000000 nop 471 032c 0F000000 sync 472 0330 0800E003 jr ra 472 00000000 473 0338 00000000 nop 474 tlbWrite1: 475 033c 06000042 tlbwr 476 0340 00000000 nop 477 0344 0F000000 sync 478 0348 0800E003 jr ra GAS LISTING /tmp/ccZtg9Qb.s page 10 478 00000000 479 0350 00000000 nop 480 481 482 .globl getCount 483 getCount: 484 0354 00480240 mfc0 v0, CP0_Count 485 0358 0800E003 jr ra 485 00000000 486 487 ######################################################################## 488 489 /* 490 * CP0 register accessors to be called from C 491 */ 492 493 #define CP0(REG) \ 494 .global cp0Rd ## REG ; \ 495 cp0Rd ## REG ## : ; \ 496 mfc0 v0,CP0_ ## REG ; \ 497 jr ra ; \ 498 nop ; \ 499 ; \ 500 .global cp0Wr ## REG ; \ 501 cp0Wr ## REG ## : ; \ 502 mtc0 a0,CP0_ ## REG ; \ 503 jr ra ; \ 504 nop 505 506 0360 00000240 CP0(Index) 506 0800E003 506 00000000 506 00000000 506 00008440 507 0380 00080240 CP0(Random) 507 0800E003 507 00000000 507 00000000 507 00088440 508 03a0 00100240 CP0(EntryLo0) 508 0800E003 508 00000000 508 00000000 508 00108440 509 03c0 00180240 CP0(EntryLo1) 509 0800E003 509 00000000 509 00000000 509 00188440 510 03e0 00200240 CP0(Context) 510 0800E003 510 00000000 510 00000000 510 00208440 511 0400 00280240 CP0(PageMask) 511 0800E003 511 00000000 GAS LISTING /tmp/ccZtg9Qb.s page 11 511 00000000 511 00288440 512 0420 00300240 CP0(Wired) 512 0800E003 512 00000000 512 00000000 512 00308440 513 0440 00400240 CP0(BadVAddr) 513 0800E003 513 00000000 513 00000000 513 00408440 514 0460 00480240 CP0(Count) 514 0800E003 514 00000000 514 00000000 514 00488440 515 0480 00500240 CP0(EntryHi) 515 0800E003 515 00000000 515 00000000 515 00508440 516 04a0 00580240 CP0(Compare) 516 0800E003 516 00000000 516 00000000 516 00588440 517 04c0 00600240 CP0(Status) 517 0800E003 517 00000000 517 00000000 517 00608440 518 04e0 00680240 CP0(Cause) 518 0800E003 518 00000000 518 00000000 518 00688440 519 0500 00700240 CP0(EPC) 519 0800E003 519 00000000 519 00000000 519 00708440 520 0520 00780240 CP0(PRId) 520 0800E003 520 00000000 520 00000000 520 00788440 521 0540 00800240 CP0(Config) 521 0800E003 521 00000000 521 00000000 521 00808440 522 0560 00800240 CP0(Config0) 522 0800E003 522 00000000 522 00000000 522 00808440 GAS LISTING /tmp/ccZtg9Qb.s page 12 523 0580 01800240 CP0(Config1) 523 0800E003 523 00000000 523 00000000 523 01808440 524 05a0 00880240 CP0(LLAddr) 524 0800E003 524 00000000 524 00000000 524 00888440 525 05c0 00900240 CP0(WatchLo) 525 0800E003 525 00000000 ⌨️ 快捷键说明
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