📄 uart.lst
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GAS LISTING /tmp/cc4XVykA.s page 1 1 .section .mdebug.abi32 2 .previous 3 .section .debug_abbrev,"",@progbits 4 $Ldebug_abbrev0: 5 .section .debug_info,"",@progbits 6 $Ldebug_info0: 7 .section .debug_line,"",@progbits 8 $Ldebug_line0: 9 0000 10010000 .text 9 0200A300 9 00000101 9 FB0E0A00 9 01010101 10 $Ltext0: 11 .local sys 12 .comm sys,4,4 13 .align 2 14 .globl uartInit 15 .ent uartInit 16 .type uartInit, @function 17 uartInit: 18 $LFB2: 19 .file 1 "/mnt/hgfs/boot/booter/source/uart.c" 1:/mnt/hgfs/boot/booter/source/uart.c **** #include "example.h" 2:/mnt/hgfs/boot/booter/source/uart.c **** 3:/mnt/hgfs/boot/booter/source/uart.c **** /********************************************************************/ 4:/mnt/hgfs/boot/booter/source/uart.c **** 5:/mnt/hgfs/boot/booter/source/uart.c **** static AU1X00_SYS *sys=NULL; 6:/mnt/hgfs/boot/booter/source/uart.c **** 7:/mnt/hgfs/boot/booter/source/uart.c **** //#define USE_UART_IRQ 8:/mnt/hgfs/boot/booter/source/uart.c **** #ifdef USE_UART_IRQ 9:/mnt/hgfs/boot/booter/source/uart.c **** #define AU1000_UART unsigned int 10:/mnt/hgfs/boot/booter/source/uart.c **** 11:/mnt/hgfs/boot/booter/source/uart.c **** #define MAX_UARTS 4 12:/mnt/hgfs/boot/booter/source/uart.c **** #define FIFO_SIZE 1024 13:/mnt/hgfs/boot/booter/source/uart.c **** 14:/mnt/hgfs/boot/booter/source/uart.c **** 15:/mnt/hgfs/boot/booter/source/uart.c **** 16:/mnt/hgfs/boot/booter/source/uart.c **** typedef volatile struct UART_t 17:/mnt/hgfs/boot/booter/source/uart.c **** { 18:/mnt/hgfs/boot/booter/source/uart.c **** AU1X00_UART *uart; 19:/mnt/hgfs/boot/booter/source/uart.c **** int uartNumber; 20:/mnt/hgfs/boot/booter/source/uart.c **** int irq; 21:/mnt/hgfs/boot/booter/source/uart.c **** int nextrx, lastrx, sizerx; 22:/mnt/hgfs/boot/booter/source/uart.c **** int nexttx, lasttx, sizetx; 23:/mnt/hgfs/boot/booter/source/uart.c **** uint32 rx, rxerr; 24:/mnt/hgfs/boot/booter/source/uart.c **** uint32 tx, txerr; 25:/mnt/hgfs/boot/booter/source/uart.c **** uint32 rxirq; 26:/mnt/hgfs/boot/booter/source/uart.c **** uint32 txirq; 27:/mnt/hgfs/boot/booter/source/uart.c **** uint32 mdmirq; 28:/mnt/hgfs/boot/booter/source/uart.c **** uint32 linirq; 29:/mnt/hgfs/boot/booter/source/uart.c **** int maxrfifo; 30:/mnt/hgfs/boot/booter/source/uart.c **** int maxtfifo; 31:/mnt/hgfs/boot/booter/source/uart.c **** uint8 rxfifo[FIFO_SIZE]; 32:/mnt/hgfs/boot/booter/source/uart.c **** uint8 txfifo[FIFO_SIZE]; 33:/mnt/hgfs/boot/booter/source/uart.c **** 34:/mnt/hgfs/boot/booter/source/uart.c **** } UART_t;GAS LISTING /tmp/cc4XVykA.s page 2 35:/mnt/hgfs/boot/booter/source/uart.c **** 36:/mnt/hgfs/boot/booter/source/uart.c **** static UART_t uarts[MAX_UARTS] = { 0 }; 37:/mnt/hgfs/boot/booter/source/uart.c **** 38:/mnt/hgfs/boot/booter/source/uart.c **** 39:/mnt/hgfs/boot/booter/source/uart.c **** /********************************************************************/ 40:/mnt/hgfs/boot/booter/source/uart.c **** void 41:/mnt/hgfs/boot/booter/source/uart.c **** uartStats (int uartNumber) 42:/mnt/hgfs/boot/booter/source/uart.c **** { 43:/mnt/hgfs/boot/booter/source/uart.c **** UART_t *p = &uarts[uartNumber]; 44:/mnt/hgfs/boot/booter/source/uart.c **** printf("UART %d:\n", uartNumber); 45:/mnt/hgfs/boot/booter/source/uart.c **** printf(" irq: %d\n", p->irq); 46:/mnt/hgfs/boot/booter/source/uart.c **** printf(" inten: %08X\n", p->uart->inten); 47:/mnt/hgfs/boot/booter/source/uart.c **** printf(" fifoctrl: %08X\n", p->uart->fifoctrl); 48:/mnt/hgfs/boot/booter/source/uart.c **** printf(" linectrl: %08X\n", p->uart->linectrl); 49:/mnt/hgfs/boot/booter/source/uart.c **** printf(" mdmctrl: %08X\n", p->uart->mdmctrl); 50:/mnt/hgfs/boot/booter/source/uart.c **** printf(" linestat: %08X\n", p->uart->linestat); 51:/mnt/hgfs/boot/booter/source/uart.c **** printf(" mdmstat: %08X\n", p->uart->mdmstat); 52:/mnt/hgfs/boot/booter/source/uart.c **** printf(" rxirq: %d\n", p->rxirq); 53:/mnt/hgfs/boot/booter/source/uart.c **** printf(" nextrx %d, lastrx %d, sizerx %d\n", 54:/mnt/hgfs/boot/booter/source/uart.c **** p->nextrx, p->lastrx, p->sizerx); 55:/mnt/hgfs/boot/booter/source/uart.c **** printf(" rx %d, rxerr %d\n", p->rx, p->rxerr); 56:/mnt/hgfs/boot/booter/source/uart.c **** printf(" maxrfifo %d\n", p->maxrfifo); 57:/mnt/hgfs/boot/booter/source/uart.c **** printf(" txirq: %d\n", p->txirq); 58:/mnt/hgfs/boot/booter/source/uart.c **** printf(" nexttx %d, lasttx %d, sizetx %d\n", 59:/mnt/hgfs/boot/booter/source/uart.c **** p->nexttx, p->lasttx, p->sizetx); 60:/mnt/hgfs/boot/booter/source/uart.c **** printf(" tx %d, txerr %d\n", p->tx, p->txerr); 61:/mnt/hgfs/boot/booter/source/uart.c **** printf(" maxtfifo %d\n", p->maxtfifo); 62:/mnt/hgfs/boot/booter/source/uart.c **** printf(" lineirq: %d\n", p->linirq); 63:/mnt/hgfs/boot/booter/source/uart.c **** printf(" mdmirq: %d\n", p->mdmirq); 64:/mnt/hgfs/boot/booter/source/uart.c **** } 65:/mnt/hgfs/boot/booter/source/uart.c **** 66:/mnt/hgfs/boot/booter/source/uart.c **** /********************************************************************/ 67:/mnt/hgfs/boot/booter/source/uart.c **** void 68:/mnt/hgfs/boot/booter/source/uart.c **** uartPutChar (int uartNumber, int ch) 69:/mnt/hgfs/boot/booter/source/uart.c **** { 70:/mnt/hgfs/boot/booter/source/uart.c **** uint32 ipl; 71:/mnt/hgfs/boot/booter/source/uart.c **** UART_t *p = &uarts[uartNumber]; 72:/mnt/hgfs/boot/booter/source/uart.c **** int spin; 73:/mnt/hgfs/boot/booter/source/uart.c **** int chs = 0; 74:/mnt/hgfs/boot/booter/source/uart.c **** 75:/mnt/hgfs/boot/booter/source/uart.c **** /* 76:/mnt/hgfs/boot/booter/source/uart.c **** * The example infrastructure has no way to "block the process" 77:/mnt/hgfs/boot/booter/source/uart.c **** * if the transmit queue is full, so must spin... 78:/mnt/hgfs/boot/booter/source/uart.c **** */ 79:/mnt/hgfs/boot/booter/source/uart.c **** if (ch >= 0) 80:/mnt/hgfs/boot/booter/source/uart.c **** { 81:/mnt/hgfs/boot/booter/source/uart.c **** spin = TRUE; 82:/mnt/hgfs/boot/booter/source/uart.c **** while (spin) 83:/mnt/hgfs/boot/booter/source/uart.c **** { 84:/mnt/hgfs/boot/booter/source/uart.c **** /* 85:/mnt/hgfs/boot/booter/source/uart.c **** * Queue manipulation is a critical section activity 86:/mnt/hgfs/boot/booter/source/uart.c **** */ 87:/mnt/hgfs/boot/booter/source/uart.c **** ipl = cpuDisableIrqs(); 88:/mnt/hgfs/boot/booter/source/uart.c **** 89:/mnt/hgfs/boot/booter/source/uart.c **** /* Enqueue the character */ 90:/mnt/hgfs/boot/booter/source/uart.c **** if (p->sizetx <= (FIFO_SIZE - 2)) 91:/mnt/hgfs/boot/booter/source/uart.c **** {GAS LISTING /tmp/cc4XVykA.s page 3 92:/mnt/hgfs/boot/booter/source/uart.c **** p->txfifo[p->nexttx] = ch; 93:/mnt/hgfs/boot/booter/source/uart.c **** p->sizetx++; 94:/mnt/hgfs/boot/booter/source/uart.c **** p->nexttx++; 95:/mnt/hgfs/boot/booter/source/uart.c **** if (p->nexttx == (FIFO_SIZE - 1)) 96:/mnt/hgfs/boot/booter/source/uart.c **** p->nexttx = 0; 97:/mnt/hgfs/boot/booter/source/uart.c **** spin = FALSE; 98:/mnt/hgfs/boot/booter/source/uart.c **** } 99:/mnt/hgfs/boot/booter/source/uart.c **** else 100:/mnt/hgfs/boot/booter/source/uart.c **** { 101:/mnt/hgfs/boot/booter/source/uart.c **** /* re-enable interrupts to allow queue to drain */ 102:/mnt/hgfs/boot/booter/source/uart.c **** cpuEnableIrqs(ipl); 103:/mnt/hgfs/boot/booter/source/uart.c **** } 104:/mnt/hgfs/boot/booter/source/uart.c **** } 105:/mnt/hgfs/boot/booter/source/uart.c **** cpuEnableIrqs(ipl); 106:/mnt/hgfs/boot/booter/source/uart.c **** } 107:/mnt/hgfs/boot/booter/source/uart.c **** 108:/mnt/hgfs/boot/booter/source/uart.c **** /* Send character(s) */ 109:/mnt/hgfs/boot/booter/source/uart.c **** if (p->uart->linestat & (UART_LINESTAT_TE | UART_LINESTAT_TT)) 110:/mnt/hgfs/boot/booter/source/uart.c **** { 111:/mnt/hgfs/boot/booter/source/uart.c **** ipl = cpuDisableIrqs(); 112:/mnt/hgfs/boot/booter/source/uart.c **** 113:/mnt/hgfs/boot/booter/source/uart.c **** /* Dequeue a character */ 114:/mnt/hgfs/boot/booter/source/uart.c **** if (p->sizetx) 115:/mnt/hgfs/boot/booter/source/uart.c **** { 116:/mnt/hgfs/boot/booter/source/uart.c **** /* Fill Tx FIFO best we can */ 117:/mnt/hgfs/boot/booter/source/uart.c **** while (p->uart->linestat & (UART_LINESTAT_TE | UART_LINESTAT_TT)) 118:/mnt/hgfs/boot/booter/source/uart.c **** { 119:/mnt/hgfs/boot/booter/source/uart.c **** ch = p->txfifo[p->lasttx]; 120:/mnt/hgfs/boot/booter/source/uart.c **** p->sizetx--; 121:/mnt/hgfs/boot/booter/source/uart.c **** p->lasttx++; 122:/mnt/hgfs/boot/booter/source/uart.c **** if (p->lasttx == (FIFO_SIZE - 1)) 123:/mnt/hgfs/boot/booter/source/uart.c **** p->lasttx = 0; 124:/mnt/hgfs/boot/booter/source/uart.c **** 125:/mnt/hgfs/boot/booter/source/uart.c **** /* send the character */ 126:/mnt/hgfs/boot/booter/source/uart.c **** p->uart->txdata = ch; 127:/mnt/hgfs/boot/booter/source/uart.c **** p->uart->inten |= UART_INTEN_TIE; 128:/mnt/hgfs/boot/booter/source/uart.c **** ++p->tx; 129:/mnt/hgfs/boot/booter/source/uart.c **** if (++chs > p->maxtfifo) p->maxtfifo = chs; 130:/mnt/hgfs/boot/booter/source/uart.c **** if (p->sizetx == 0) break; /* no more chars */ 131:/mnt/hgfs/boot/booter/source/uart.c **** } 132:/mnt/hgfs/boot/booter/source/uart.c **** } 133:/mnt/hgfs/boot/booter/source/uart.c **** else 134:/mnt/hgfs/boot/booter/source/uart.c **** { 135:/mnt/hgfs/boot/booter/source/uart.c **** /* nothing to send, disable Tx IRQ */ 136:/mnt/hgfs/boot/booter/source/uart.c **** //p->uart->inten &= ~UART_INTEN_TIE; 137:/mnt/hgfs/boot/booter/source/uart.c **** /* fix!!! doing this causes Tx stalls */ 138:/mnt/hgfs/boot/booter/source/uart.c **** } 139:/mnt/hgfs/boot/booter/source/uart.c **** 140:/mnt/hgfs/boot/booter/source/uart.c **** cpuEnableIrqs(ipl); 141:/mnt/hgfs/boot/booter/source/uart.c **** } 142:/mnt/hgfs/boot/booter/source/uart.c **** } 143:/mnt/hgfs/boot/booter/source/uart.c **** 144:/mnt/hgfs/boot/booter/source/uart.c **** /********************************************************************/ 145:/mnt/hgfs/boot/booter/source/uart.c **** void 146:/mnt/hgfs/boot/booter/source/uart.c **** uartGetChar (int uartNumber, int *ch) 147:/mnt/hgfs/boot/booter/source/uart.c **** { 148:/mnt/hgfs/boot/booter/source/uart.c **** uint32 ipl;GAS LISTING /tmp/cc4XVykA.s page 4 149:/mnt/hgfs/boot/booter/source/uart.c **** int c, chs = 0; 150:/mnt/hgfs/boot/booter/source/uart.c **** UART_t *p = &uarts[uartNumber]; 151:/mnt/hgfs/boot/booter/source/uart.c **** 152:/mnt/hgfs/boot/booter/source/uart.c **** if ((p->sizerx == 0) && (ch != NULL)) 153:/mnt/hgfs/boot/booter/source/uart.c **** { 154:/mnt/hgfs/boot/booter/source/uart.c **** /* We must wait for a character to arrive...this example 155:/mnt/hgfs/boot/booter/source/uart.c **** code doesn't have the ability to "block a process" */ 156:/mnt/hgfs/boot/booter/source/uart.c **** //while ((p->uart->linestat & UART_LINESTAT_DR) == 0) ; 157:/mnt/hgfs/boot/booter/source/uart.c **** while (p->sizerx == 0) ; 158:/mnt/hgfs/boot/booter/source/uart.c **** } 159:/mnt/hgfs/boot/booter/source/uart.c **** 160:/mnt/hgfs/boot/booter/source/uart.c **** /* 161:/mnt/hgfs/boot/booter/source/uart.c **** * Queue manipulation is a critical section activity 162:/mnt/hgfs/boot/booter/source/uart.c **** */ 163:/mnt/hgfs/boot/booter/source/uart.c **** ipl = cpuDisableIrqs(); 164:/mnt/hgfs/boot/booter/source/uart.c **** 165:/mnt/hgfs/boot/booter/source/uart.c **** /* Extract all characters received */ 166:/mnt/hgfs/boot/booter/source/uart.c **** while (p->uart->linestat & UART_LINESTAT_DR) 167:/mnt/hgfs/boot/booter/source/uart.c **** { 168:/mnt/hgfs/boot/booter/source/uart.c **** ++chs; 169:/mnt/hgfs/boot/booter/source/uart.c **** c = (p->uart->rxdata & 0x00FF); 170:/mnt/hgfs/boot/booter/source/uart.c **** ++p->rx; 171:/mnt/hgfs/boot/booter/source/uart.c **** 172:/mnt/hgfs/boot/booter/source/uart.c **** /* Enqueue the character */ 173:/mnt/hgfs/boot/booter/source/uart.c **** if (p->sizerx <= (FIFO_SIZE - 2)) 174:/mnt/hgfs/boot/booter/source/uart.c **** { 175:/mnt/hgfs/boot/booter/source/uart.c **** p->rxfifo[p->nextrx] = c; 176:/mnt/hgfs/boot/booter/source/uart.c **** p->sizerx++; 177:/mnt/hgfs/boot/booter/source/uart.c **** p->nextrx++; 178:/mnt/hgfs/boot/booter/source/uart.c **** if (p->nextrx == (FIFO_SIZE - 1)) 179:/mnt/hgfs/boot/booter/source/uart.c **** p->nextrx = 0; 180:/mnt/hgfs/boot/booter/source/uart.c **** } 181:/mnt/hgfs/boot/booter/source/uart.c **** else ++p->rxerr; 182:/mnt/hgfs/boot/booter/source/uart.c **** /* else character is dropped! */ 183:/mnt/hgfs/boot/booter/source/uart.c **** } 184:/mnt/hgfs/boot/booter/source/uart.c **** 185:/mnt/hgfs/boot/booter/source/uart.c **** if (chs > p->maxrfifo) p->maxrfifo = chs; 186:/mnt/hgfs/boot/booter/source/uart.c **** 187:/mnt/hgfs/boot/booter/source/uart.c **** /* Dequeue a character */ 188:/mnt/hgfs/boot/booter/source/uart.c **** if (ch != NULL) 189:/mnt/hgfs/boot/booter/source/uart.c **** { 190:/mnt/hgfs/boot/booter/source/uart.c **** *ch = p->rxfifo[p->lastrx]; 191:/mnt/hgfs/boot/booter/source/uart.c **** p->sizerx--; 192:/mnt/hgfs/boot/booter/source/uart.c **** p->lastrx++; 193:/mnt/hgfs/boot/booter/source/uart.c **** if (p->lastrx == (FIFO_SIZE - 1)) 194:/mnt/hgfs/boot/booter/source/uart.c **** p->lastrx = 0; 195:/mnt/hgfs/boot/booter/source/uart.c **** } 196:/mnt/hgfs/boot/booter/source/uart.c **** 197:/mnt/hgfs/boot/booter/source/uart.c **** cpuEnableIrqs(ipl); 198:/mnt/hgfs/boot/booter/source/uart.c **** } 199:/mnt/hgfs/boot/booter/source/uart.c **** 200:/mnt/hgfs/boot/booter/source/uart.c **** /********************************************************************/ 201:/mnt/hgfs/boot/booter/source/uart.c **** int 202:/mnt/hgfs/boot/booter/source/uart.c **** uartCheckChar (int uartNumber) 203:/mnt/hgfs/boot/booter/source/uart.c **** { 204:/mnt/hgfs/boot/booter/source/uart.c **** UART_t *p = &uarts[uartNumber]; 205:/mnt/hgfs/boot/booter/source/uart.c **** uint32 ipl;GAS LISTING /tmp/cc4XVykA.s page 5 206:/mnt/hgfs/boot/booter/source/uart.c **** int value; 207:/mnt/hgfs/boot/booter/source/uart.c **** 208:/mnt/hgfs/boot/booter/source/uart.c **** /* 209:/mnt/hgfs/boot/booter/source/uart.c **** * Queue manipulation is a critical section activity 210:/mnt/hgfs/boot/booter/source/uart.c **** */ 211:/mnt/hgfs/boot/booter/source/uart.c **** ipl = cpuDisableIrqs(); 212:/mnt/hgfs/boot/booter/source/uart.c **** 213:/mnt/hgfs/boot/booter/source/uart.c **** if (p->sizerx) 214:/mnt/hgfs/boot/booter/source/uart.c **** value = TRUE; 215:/mnt/hgfs/boot/booter/source/uart.c **** else 216:/mnt/hgfs/boot/booter/source/uart.c **** value = FALSE; 217:/mnt/hgfs/boot/booter/source/uart.c **** 218:/mnt/hgfs/boot/booter/source/uart.c **** cpuEnableIrqs(ipl); 219:/mnt/hgfs/boot/booter/source/uart.c **** 220:/mnt/hgfs/boot/booter/source/uart.c **** return value; 221:/mnt/hgfs/boot/booter/source/uart.c **** } 222:/mnt/hgfs/boot/booter/source/uart.c **** 223:/mnt/hgfs/boot/booter/source/uart.c **** /********************************************************************/ 224:/mnt/hgfs/boot/booter/source/uart.c **** void 225:/mnt/hgfs/boot/booter/source/uart.c **** uartHandler (int irqNumber, UART_t *p) 226:/mnt/hgfs/boot/booter/source/uart.c **** { 227:/mnt/hgfs/boot/booter/source/uart.c **** volatile uint32 intcause, linestat, mdmstat; 228:/mnt/hgfs/boot/booter/source/uart.c **** 229:/mnt/hgfs/boot/booter/source/uart.c **** intcause = p->uart->intcause; 230:/mnt/hgfs/boot/booter/source/uart.c **** switch (intcause & UART_INTCAUSE_IID) 231:/mnt/hgfs/boot/booter/source/uart.c **** { 232:/mnt/hgfs/boot/booter/source/uart.c **** case UART_INTCAUSE_IID_TBA: /* tx buffer available */ 233:/mnt/hgfs/boot/booter/source/uart.c **** ++p->txirq; 234:/mnt/hgfs/boot/booter/source/uart.c **** uartPutChar(p->uartNumber, -1); 235:/mnt/hgfs/boot/booter/source/uart.c **** break; 236:/mnt/hgfs/boot/booter/source/uart.c **** case UART_INTCAUSE_IID_RDA: /* rx data available */ 237:/mnt/hgfs/boot/booter/source/uart.c **** case UART_INTCAUSE_IID_CTO: /* char time out */ 238:/mnt/hgfs/boot/booter/source/uart.c **** ++p->rxirq; 239:/mnt/hgfs/boot/booter/source/uart.c **** uartGetChar(p->uartNumber, NULL); 240:/mnt/hgfs/boot/booter/source/uart.c **** break; 241:/mnt/hgfs/boot/booter/source/uart.c **** case UART_INTCAUSE_IID_MS: /* modem status change */ 242:/mnt/hgfs/boot/booter/source/uart.c **** mdmstat = p->uart->mdmstat; 243:/mnt/hgfs/boot/booter/source/uart.c **** ++p->mdmirq; 244:/mnt/hgfs/boot/booter/source/uart.c **** break; 245:/mnt/hgfs/boot/booter/source/uart.c **** case UART_INTCAUSE_IID_RLS: /* line status change */ 246:/mnt/hgfs/boot/booter/source/uart.c **** linestat = p->uart->linestat; 247:/mnt/hgfs/boot/booter/source/uart.c **** ++p->linirq; 248:/mnt/hgfs/boot/booter/source/uart.c **** break; 249:/mnt/hgfs/boot/booter/source/uart.c **** default:
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