reset.lst

au1200下的boot代码

 872              	
 873              	/************************************************************************/
 874              	
 875              	hardwarereset:
 876              	runtimereset:
 877              	hibernatereset:
 878              		/*
 879              		 * Step 1) Initialize DRAM
 880              		 * Step 2) Initialize board
 881              		 * Step 3) Invoke application
 882              		 */
 883 0348 0E001104 		bal 	initDRAM
 884 034c 00000000 		nop 
 885 0350 A5001104 	   	bal	initBOARD
 886 0354 00000000 		nop
 887 0358 A5000010 		b	alldone
 888 035c 00000000 		nop	 
 889              	
 890              	sleepwakeup:
 891              		/*
 892              		 * Step 1) Wakeup DRAM
 893              		 * Step 2) Initialize board
 894              		 * Step 3) Resume application
 895              		 */
 896 0360 79001104 	  	bal	wakeupDRAM	
 897 0364 00000000 	  	nop
 898 0368 9F001104 		bal	initBOARD
 899 036c 00000000 		nop
 900 0370 90B1083C 		la	t0, AU1200_SYS_ADDR
 901 0374 18001D8D 		lw	sp, sys_scratch0(t0)
GAS LISTING /tmp/ccxobHen.s 			page 18


 902 0378 1C001F8D 		lw	ra, sys_scratch1(t0)
 903 037c 0800E003 		jr	ra
 904 0380 00000000 		nop
 905              	
 906              	/*************************************************************************/
 907              	
 908              	initDRAM:
 909              	
 910              		/* Only perform DRAM init if running from ROM/Flash */
 911 0384 2150E003 		addu	t2, ra, zero	/* preserve ra */
 912 0388 01000010 		b	getPC
 913 038c 00000000 	 	nop
 914              	
 915              	getPC:
 916 0390 001F083C 		lui	t0, 0x1F00      /* ROM/flash address? */
 917 0394 24481F01 		and	t1, t0, ra
 918 0398 21F84001 		addu	ra, t2, zero	/* restore ra */
 919 039c 57000915 		bne	t0, t1, initDDRdone
 920 03a0 00000000 		nop
 921              	
 922              		/* wait 1mS before setup */
 923 03a4 0600093C 		li	t1, MEM_1MS
 923      E00A2935 
 924 03ac FFFF2921 	1:	addi	t1, t1, -1
 925 03b0 FEFF2015 		bne	t1, zero, 1b
 926 03b4 00000000 		nop
 927              	
 928              	initDDR2:
 929 03b8 E011093C 		li	t1, MEM_SDCONFIGA_DDR2
 929      0A062935 
 930 03c0 02A00A3C 		li	t2, MEM_SDCONFIGB_DDR2
 930      0C614A35 
 931 03c8 28010B3C 		li	t3, MEM_SDMODE0_DDR2
 931      34336B35 
 932 03d0 28010C3C 		li	t4, MEM_SDMODE1_DDR2
 932      34338C35 
 933 03d8 32040224 		li	v0, MEM_MR0_DDR2
 934 03dc 0040033C 		li	v1, MEM_MR1_DDR2
 934      00046334 
 935 03e4 10220D3C 		li	t5, MEM_SDADDR0_DDR2
 935      F003AD35 
 936 03ec 0F010E3C 		li	t6, MEM_SDADDR1_DDR2
 936      FFFFCE35 
 937 03f4 0080063C 		li	a2, MEM_MR2_DDR2
 938 03f8 00C0073C 		li	a3, MEM_MR3_DDR2
 939              	
 940 03fc 00B4083C 		li	t0, AU1200_MEM_ADDR
 941 0400 0800013C 		or	t2, MEM_SDCONFIGB_BB /* block LCD/MAE during init */
 941      25504101 
 942 0408 400809AD 		sw	t1, mem_sdconfiga(t0)
 943 040c 0F000000 		sync
 944 0410 48080AAD 		sw	t2, mem_sdconfigb(t0)
 945 0414 0F000000 		sync
 946 0418 00080BAD 		sw	t3, mem_sdmode0(t0)
 947 041c 08080CAD 		sw	t4, mem_sdmode1(t0)
 948 0420 20080DAD 		sw	t5, mem_sdaddr0(t0)
 949 0424 28080EAD 		sw	t6, mem_sdaddr1(t0)
GAS LISTING /tmp/ccxobHen.s 			page 19


 950 0428 0F000000 		sync
 951              	
 952              		/*
 953              		 * Initialization per Micron data sheet, page 72:
 954              		 * 0. Power sequence
 955              		 * 1. 200us delay
 956              		 * 2. NOP w/ CKE
 957              		 * 3. 400ns delay
 958              		 * 4. PRECHARGE ALL
 959              		 * 5. EMRS(3), EMRS(2)
 960              		 * 6. EMRS(1) (DLL enable, OCD)
 961              		 * 7. EMRS (DLL reset activated)
 962              		 * 8. 200 clocks of idle
 963              		 * 9. PRECHARGE ALL
 964              		 * 10. AUTO REFRESH x 2
 965              		 * 11. EMRS (DLL reset de-activated)
 966              		 * Devices are now ready for use.
 967              		 */
 968              	
 969              		/* NOP w/ CKE */
 970 042c 4808098D 		lw	t1, mem_sdconfigb(t0)
 971 0430 80000A24 		li	t2, MEM_SDCONFIGB_BA
 972 0434 25484901 		or	t1, t2, t1
 973 0438 480809AD 		sw	t1, mem_sdconfigb(t0)
 974 043c 0F000000 		sync
 975              	
 976              		/* wait 400nS */
 977 0440 9E000924 		li	t1, MEM_400NS
 978 0444 FFFF2921 	2:	addi	t1, t1, -1
 979 0448 FEFF2015 		bne	t1, zero, 2b
 980 044c 00000000 		nop
 981              	
 982              		/* PRECHARGE ALL */
 983 0450 C00800AD 		sw	zero, mem_sdprecmd(t0)
 984 0454 0F000000 		sync
 985              	
 986              		/* LOAD MODE REGISTER extended mode register 3 */
 987 0458 800807AD 		sw	a3, mem_sdwrmd0(t0)		
 988 045c 0F000000 		sync
 989 0460 880807AD 		sw	a3, mem_sdwrmd1(t0)		
 990 0464 0F000000 		sync
 991              	
 992              		/* LOAD MODE REGISTER extended mode register 2 */
 993 0468 800806AD 		sw	a2, mem_sdwrmd0(t0)		
 994 046c 0F000000 		sync
 995 0470 880806AD 		sw	a2, mem_sdwrmd1(t0)		
 996 0474 0F000000 		sync
 997              	
 998              		/* LOAD MODE REGISTER extended mode register 1 */
 999 0478 800803AD 		sw	v1, mem_sdwrmd0(t0)		
 1000 047c 0F000000 		sync
 1001 0480 800803AD 		sw	v1, mem_sdwrmd0(t0)		
 1002 0484 0F000000 		sync
 1003              	
 1004              		/* LOAD MODE REGISTER normal mode register DLL reset */
 1005              	#define MR0_DLL 0x0100
 1006 0488 00014934 		ori	t1, v0, MR0_DLL
GAS LISTING /tmp/ccxobHen.s 			page 20


 1007 048c 800809AD 		sw	t1, mem_sdwrmd0(t0)
 1008 0490 0F000000 		sync
 1009 0494 880809AD 		sw	t1, mem_sdwrmd1(t0)
 1010 0498 0F000000 		sync
 1011              	
 1012              		/* 200 clocks of idle */
 1013 049c 4808098D 		lw	t1, mem_sdconfigb(t0)
 1014 04a0 80000A24 		li	t2, MEM_SDCONFIGB_BA
 1015 04a4 25484901 		or	t1, t2, t1
 1016 04a8 480809AD 		sw	t1, mem_sdconfigb(t0)
 1017 04ac 0F000000 		sync
 1018              	
 1019              		/* PRECHARGE ALL */
 1020 04b0 C00800AD 		sw	zero, mem_sdprecmd(t0)
 1021 04b4 0F000000 		sync
 1022              	
 1023              		/* AUTO REFRESH x 2 */
 1024 04b8 C80800AD 		sw	zero, mem_sdautoref(t0)
 1025 04bc 0F000000 		sync
 1026 04c0 C80800AD 		sw	zero, mem_sdautoref(t0)
 1027 04c4 0F000000 		sync
 1028              	
 1029              		/* LOAD MODE REGISTER normal mode register */
 1030 04c8 800802AD 		sw	v0, mem_sdwrmd0(t0)
 1031 04cc 0F000000 		sync
 1032 04d0 880802AD 		sw	v0, mem_sdwrmd1(t0)
 1033 04d4 0F000000 		sync
 1034              	
 1035              		/* LOAD MODE REGISTER extended mode register 1 */
 1036              	#define MR1_OCD_DEFAULT 0x0380
 1037 04d8 80036934 		ori	t1, v1, MR1_OCD_DEFAULT
 1038 04dc 800809AD 		sw	t1, mem_sdwrmd0(t0)
 1039 04e0 0F000000 		sync
 1040 04e4 880809AD 		sw	t1, mem_sdwrmd1(t0)
 1041 04e8 0F000000 		sync
 1042 04ec 800803AD 		sw	v1, mem_sdwrmd0(t0)
 1043 04f0 0F000000 		sync
 1044 04f4 880803AD 		sw	v1, mem_sdwrmd1(t0)
 1045 04f8 0F000000 		sync
 1046              	
 1047              	initDDRdone:
 1048              		/* Enable refresh */
 1049 04fc 00B4083C 		li	t0, AU1200_MEM_ADDR
 1050 0500 4008098D 		lw	t1, mem_sdconfiga(t0)
 1051 0504 00800A3C 		li	t2, MEM_SDCONFIGA_E
 1052 0508 25484901 		or	t1, t2, t1
 1053 050c 400809AD 		sw	t1, mem_sdconfiga(t0)
 1054 0510 0F000000 		sync
 1055              	
 1056              		/* Allow MAE/LCD */
 1057 0514 4808098D 		lw	t1, mem_sdconfigb(t0)
 1058 0518 F7FF0A3C 		li	t2, ~MEM_SDCONFIGB_BB
 1058      FFFF4A35 
 1059 0520 24484901 		and	t1, t2, t1
 1060 0524 480809AD 		sw	t1, mem_sdconfigb(t0)
 1061 0528 0F000000 		sync
 1062              	
GAS LISTING /tmp/ccxobHen.s 			page 21


 1063              		/* wait 1mS after setup */
 1064 052c 0600093C 		li	t1, MEM_1MS
 1064      E00A2935 
 1065 0534 FFFF2921 	1:	addi	t1, t1, -1
 1066 0538 FEFF2015 		bne	t1, zero, 1b
 1067 053c 00000000 		nop
 1068              	
 1069 0540 0800E003 		jr		ra
 1070 0544 00000000 		nop
 1071              	
 1072              	
 1073              	/********************************************************************/
 1074              	
 1075              	wakeupDRAM:	
 1076              	
 1077 0548 E011093C 		li	t1, MEM_SDCONFIGA_DDR2
 1077      0A062935 
 1078 0550 02A00A3C 		li	t2, MEM_SDCONFIGB_DDR2
 1078      0C614A35 
 1079 0558 28010B3C 		li	t3, MEM_SDMODE0_DDR2
 1079      34336B35 
 1080 0560 28010C3C 		li	t4, MEM_SDMODE1_DDR2
 1080      34338C35 
 1081 0568 10220D3C 		li	t5, MEM_SDADDR0_DDR2
 1081      F003AD35 
 1082 0570 0F010E3C 		li	t6, MEM_SDADDR1_DDR2
 1082      FFFFCE35 
 1083              	
 1084 0578 00B4083C 		li	t0, AU1200_MEM_ADDR
 1085 057c 400809AD 		sw	t1, mem_sdconfiga(t0)
 1086 0580 0F000000 		sync
 1087 0584 48080AAD 		sw	t2, mem_sdconfigb(t0)
 1088 0588 0F000000 		sync
 1089 058c 00080BAD 		sw	t3, mem_sdmode0(t0)
 1090 0590 08080CAD 		sw	t4, mem_sdmode1(t0)
 1091 0594 20080DAD 		sw	t5, mem_sdaddr0(t0)
 1092 0598 28080EAD 		sw	t6, mem_sdaddr1(t0)
 1093 059c 0F000000 		sync
 1094              	
 1095              		/* Assert DCKE - bring DDR out of self refresh */
 1096              		/* Note that two mem_sdsref are needed since state lost during sleep 		*/
 1097 05a0 D00800AD 		sw	zero, mem_sdsref(t0)
 1098 05a4 D00800AD 		sw	zero, mem_sdsref(t0)
 1099              	
 1100              		/*
 1101              		 * Issue 80ns of NOPs
 1102              		 */ 
 1103 05a8 4808098D 		lw	t1, mem_sdconfigb(t0)
 1104 05ac 80000A24 		li	t2, MEM_SDCONFIGB_BA
 1105 05b0 25484901 		or	t1, t2, t1
 1106 05b4 480809AD 	 	sw	t1, mem_sdconfigb(t0)
 1107 05b8 0F000000 		sync 
 1108              	
 1109              		/*
 1110              		 * Perform burst refresh of 8K rows
 1111              		 */
 1112 05bc 00200924 		li	t1, 8192
GAS LISTING /tmp/ccxobHen.s 			page 22


 1113              	burstrefresh:
 1114 05c0 C80800AD 		sw	zero, mem_sdautoref(t0)
 1115 05c4 FEFF0914 		bne	zero, t1, burstrefresh
 1116 05c8 FFFF2921 		addi	t1, t1, -1
 1117              	
 1118              		/* Enable refresh */
 1119 05cc 4008098D 		lw	t1, mem_sdconfiga(t0)
 1120 05d0 00800A3C 		li	t2, MEM_SDCONFIGA_E
 1121 05d4 25484901 		or	t1, t2, t1
 1122 05d8 400809AD 		sw	t1, mem_sdconfiga(t0)
 1123 05dc 0F000000 		sync
 1124              	
 1125 05e0 0800E003 	 	jr	ra
 1126 05e4 00000000 		nop
 1127              	
 1128              	/********************************************************************/
 1129              	
 1130              	initBOARD:
 1131              	
 1132              		/*
 1133              		 * External and/or board-specific peripheral initialization
 1134              		 */
 1135              	
 1136              		/* Take IDE/LAN/DC/CIM out of reset */
 1137              	/*
 1138              		li	t0, DB1200_BCSR_ADDR
 1139              		lh	t1, bcsr_resets(t0)
 1140              		ori	t1, 0x000F
 1141              		sh	t1, bcsr_resets(t0)
 1142              		sync
 1143              	*/
 1144 05e8 0800E003 		jr	ra
 1145 05ec 00000000 		nop
 1146              	
 1147              	/********************************************************************/
 1148              	
 1149              	alldone:
 1150              	
 1151              		/*
 1152              		 * Prepare to invoke application main()
 1153              		 */
 1154              		 .set reorder
 1155              	
  33              	#endif
  11              	resetsdram:
  12 05f0 00000424 		la a0, 0
  13 05f4 0000083C 		la t0, start
  13      00000825 
  14 05fc 08000001 		jr t0
  14      00000000 
  15 0604 00000000 		nop
  15      00000000 
  15      00000000