📄 reset.lst
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263 Tcsoff= (1+6 clocks) match Tcsh 264 Twp= (1+6 clocks) data sheet specs 35ns for tWP 265 Tcsw= (1+0 clocks) data sheet specs 0ns for tCS 266 Tpm= (1+7 clocks) data sheet specs 40ns for tPACC 267 Ta= (1+23 clocks) data sheet specs 120ns for tRC 268 269 mem_stcfg0: 0000 0000 0010 1101 0000 0000 0100 0011 : 0x002D0043 270 Tcsoe=000 (see above) 271 Toecs=000 (see above) 272 AH=0 (not needed) 273 NW=0 (n/a) 274 AS=1 (setup needed) 275 S=0 (asynchronous) 276 DE=1 (de-assert) 277 MBSa=1 278 MBC=0 279 TA=1 (Tcsh for reads and writes) 280 DIV=000 (n/a) 281 ALD=0 (address latch enable) 282 AV=0 (no address visibility) 283 BE=0 (little endian) 284 TS=0 (asynchronous operation) 285 EW=0 (n/a) 286 MBSb=1 287 BS=0 (n/a) 288 PM=0 (disable page mode) 289 RO=0 (writable) 290 DTY=3 (NOR Flash) 291 292 mem_sttime0: 0000 0110 0110 0001 1000 0001 1001 0101 : 0x06618195 GAS LISTING /tmp/ccxobHen.s page 7 293 Twcs=000 294 Tcsh=0110 295 Tcsoff=110 296 Twp=000110 297 Tcsw=0000 298 Tpm=0111 299 Ta=010111 300 */ 301 #define MEM_STCFG0 0x002D0043 /* 16-bit little-endian */ 302 #define MEM_STTIME0 0x066181D7 303 #define MEM_STADDR0 0x11C03F00 /* 64MB address space */ 304 305 /* RCE1: x8 NAND Flash */ 306 #define MEM_STCFG1 0x00420045 307 #define MEM_STTIME1 0x00007774 308 #define MEM_STADDR1 0x12003FFF 309 310 /* RCE2: IDE PIOmode4 311 312 Tcsoe=MAX( 0ns, 20ns, 25ns) = (1+4 clocks) AS=1 313 Toecs=MAX( 0ns, 5ns, 10ns) = (1+1 clocks) AH=1 314 Twcs=MAX( 0ns, 5ns, 10ns) = (1+1 clocks) 315 Tcsh=MAX(10ns, 20ns, 25ns) = (1+4 clocks) 316 Tcsoff=MAX(10ns, 20ns, 25ns) = (1+4 clocks) 317 Twp=MAX(15ns, 20ns, 70ns) = (1+13 clocks) 318 Tcsw=MAX(10ns, 20ns, 20ns) = (1+3 clocks) 319 Tpm=MAX( 0ns, 0ns, 25/0ns) = (1+0 clocks) 320 Ta=MAX( 5ns, 35ns, 95ns) = (1+18 clocks) 321 322 mem_stcfg2: 1000 0110 0010 1101 0000 0000 1100 0110 : 0x862D00C6 323 Tcsoe=100 (see above) 324 Toecs=001 (see above) 325 AH=1 (hold needed) 326 NW=0 (n/a) 327 AS=1 (setup needed) 328 S=0 (asynchronous) 329 DE=1 (de-assert) 330 MBSa=1 331 MBC=0 332 TA=1 (Tcsh for reads and writes) 333 BE=0 (little endian) 334 TS=0 (asynchronous operation) 335 EW=1 (absolutely needed) 336 MBSb=1 337 BS=0 (n/a) 338 PM=0 (disable page mode) 339 RO=0 (writable) 340 DTY=6 (IDE) 341 342 mem_sttime2: 0001 0100 0100 0011 0100 1100 0001 0010 : 0x14434C12 343 Twcs=001 344 Tcsh=0100 345 Tcsoff=100 346 Twp=001101 347 Tcsw=0011 348 Tpm=0000 349 Ta=010010 GAS LISTING /tmp/ccxobHen.s page 8 350 */ 351 #define MEM_STCFG2 0x862D00C6 352 #define MEM_STTIME2 0x14434C12 353 #define MEM_STADDR2 0x11803f00 354 355 /* RCE3: PCMCIA 250ns */ 356 #define MEM_STCFG3 0x00040042 357 #define MEM_STTIME3 0x280E3E07 358 #define MEM_STADDR3 0x10000000 359 360 #define MEM_SDCONFIGA_E (1<<31) 361 #define MEM_SDCONFIGA_CE (3<<28) 362 #define MEM_SDCONFIGB_BB (1<<19) 363 #define MEM_SDCONFIGB_BA (1<<7) 364 #define MEM_SDCONFIGB_PM (2<<22) 365 366 /* 367 * SDCS0: 1:32MB gDDR2 Hynix HY5Ps561621AFP x 2 or 368 2:64MB gDDR2 Hynix HY5PS121621BFP x 1 369 SDCS1: None 370 371 With a DDR clock of 198MHz (sdconfigb[CR]=1), DDR clock period is 5ns 372 373 mem_sdmode: 0000 0001 0010 0111 0010 0010 0010 0100 : 0x01283334 374 Twtr=001 (1+1 clocks) data sheet specs 7.5ns for tWTR 375 Twr=010 (1+2 clocks) data sheet specs 15ns for tWR 376 Tras=1000 (1+8 clocks) data sheet specs 45ns for tRAS 377 Trp=011 (1+3 clocks) data sheet specs 16ns for tRP 378 Trcdwr=011 (1+3 clocks) data sheet specs 16ns for tRCD 379 Trcdrd=011 (1+3 clocks) data sheet specs 16ns for tRCD 380 Tcas=100 (CL=3 ) data sheet specs CL=3 for 400mhz 381 382 mem_sdaddr: 1:0010 0010 0001 0000 0000 0011 1110 0000 : 0x221003F0 383 BR=0 (bank,row,col) 384 RS=10 (13 row) 385 CS=010 (9 col) 386 E=1 (enabled) 387 CSBA=0000000000 (0x00000000) 388 CSMASK=1111110000 (0xFC000000) 389 2:0010 0011 0001 0000 0000 0011 1110 0000 : 0x231003F0 390 BR=0 (bank,row,col) 391 RS=10 (13 row) 392 CS=011 (10 col) 393 E=1 (enabled) 394 CSBA=0000000000 (0x00000000) 395 CSMASK=1111110000 (0xFC000000) 396 397 mem_sdconfiga: 0011 0001 1110 0000 0000 0110 0000 1010 : 0x31E0060A 398 E=0 (refresh disable) 399 CE=11 (both clocks enabled) 400 RPT=00 (1 refresh per cycle) 401 Trc=011110 (1+30 clocks) data sheet specs 61ns for tRC 402 REF=0x60A (1562 clocks) data sheet specs 7.8us 403 404 mem_sdconfigb: 1:1010 0000 0000 0010 0000 0000 0000 0000 : 0xA002610C 405 2:1110 0000 0000 0010 0000 0000 0000 0000 : 0xE002610C 406 CR=1 (1:1) GAS LISTING /tmp/ccxobHen.s page 9 407 BW=0 (32bit wide bus) 408 MT=1 (DDR2) 409 PSEL=0 (addr 10 for auto precharge) 410 C2=0 (core lowest priority) 411 AC=00 (default) 412 HP=0 (no half-pll mode) 413 PM=00 (no power modes) 414 CKECNT=00 (n/a) 415 BB=0 (normal) 416 DS=1 (full drive strength) 417 FS=0 (normal) 418 PDX=01 (2) 419 CKEmin=10 (3) 420 CB=0 (normal) 421 TXARD=001 (2) 422 BA=0 (no block) 423 TXSR=001100 (1+12 * 16=208 > 200 clocks) 424 425 mem_sdwrmd: 426 Mode Register 0: 0000 0100 0011 0010 : 0x0432 427 PD=0 Fast Exit 428 WR=010 3 Clocks 429 DLL=0 Normal 430 TM=0 Normal 431 CL=011 CL=3 432 BT=0 sequential burst type 433 BL=010 burst length of 4 434 435 Mode Register 1: 1:0000 0100 0100 0000 : 0x0440 436 2:0000 0100 0000 0000 : 0x0400 437 OUT=0 Normal drive strength 438 RDQS=0 Disable 439 DQS=1 Disable 440 OCD=000 Not supported 441 RTT=10 150 Ohm termination needed with two ranks populated 442 AL=00 0 443 ODS=0 100% 444 DLL=0 Normal/Enable 445 446 Mode Register 2: 0x0000 447 Mode Register 3: 0x0000 448 */ 449 #define MEM_SDMODE0_DDR2 0x01283334 450 #define MEM_SDMODE1_DDR2 0x01283334 451 #define MEM_SDADDR0_DDR2 0x221003F0 452 #define MEM_SDADDR1_DDR2 0x010FFFFF 453 #define MEM_SDCONFIGA_DDR2 0x11E0060A 454 #define MEM_SDCONFIGB_DDR2 0xA002610C 455 #define MEM_MR0_DDR2 0x00000432 456 #define MEM_MR1_DDR2 0x40000400 457 #define MEM_MR2_DDR2 0x80000000 458 #define MEM_MR3_DDR2 0xC0000000 459 460 /* 461 * SDCS0 - 128MB DDR2-533 Samsung K4T51163QB-GCD5 (8Mbit x 16 x 4bank x 2devices) 462 * SDCS1 - 128MB DDR2-533 Samsung K4T51163QB-GCD5 (8Mbit x 16 x 4bank x 2devices) 463 GAS LISTING /tmp/ccxobHen.s page 10 464 With a DDR clock of 198MHz (sdconfigb[CR]=1), DDR clock period is 5ns 465 466 mem_sdmode: 0000 0001 0010 0111 0010 0010 0010 0100 : 0x01272224 467 Twtr=001 (1+1 clocks) data sheet specs 10ns for tWTR 468 Twr=010 (1+2 clocks) data sheet specs 15ns for tWR 469 Tras=0111 (1+7 clocks) data sheet specs 40ns for tRAS 470 Trp=010 (1+2 clocks) data sheet specs 15ns for tRP 471 Trcdwr=010 (1+2 clocks) data sheet specs 15ns for tRCD 472 Trcdrd=010 (1+2 clocks) data sheet specs 15ns for tRCD 473 Tcas=100 (CL=3 ) data sheet specs CL=3 for 400mhz 474 475 mem_sdaddr: 0010 0011 0001 0000 0000 0011 1110 0000 : 0x231003E0 476 BR=0 (bank,row,col) 477 RS=10 (13 row) 478 CS=011 (10 col) 479 E=1 (enabled) 480 CSBA=0000000000 (0x00000000) 481 CSMASK=1111100000 (0xF8000000) 482 483 mem_sdconfiga: 0011 0001 0100 0000 0000 0110 0000 1010 : 0x3140060A 484 E=0 (refresh disable) 485 CE=11 (both clocks enabled) 486 RPT=00 (1 refresh per cycle) 487 Trc=010100 (1+20 clocks) data sheet specs 55ns for tRC, 105ns for tRFC 488 REF=0x60A (1546 clocks) data sheet specs 7.8125us intervals (8K rows in 64ms) 489 490 mem_sdconfigb: 1010 0000 0000 0010 0000 0000 0000 0000 : 0xA012610C 491 CR=1 (1:1) 492 BW=0 (32bit wide bus) 493 MT=1 (DDR2) 494 PSEL=0 (addr 10 for auto precharge) 495 C2=0 (core lowest priority) 496 AC=00 (default) 497 HP=0 (no half-pll mode) 498 PM=00 (no power modes) 499 CKECNT=01 (1*16) 500 BB=0 (normal) 501 DS=1 (full strength) 502 FS=0 (normal) 503 PDX=01 (2) 504 CKEmin=10 (3) 505 CB=0 (normal) 506 TXARD=001 (2) 507 BA=0 (no block) 508 TXSR=001100 (1+12 * 16=208 > 200 clocks) 509 510 mem_sdwrmd: 511 Mode Register 0: 0000 0100 0011 0010 : 0x0432 512 PD=0 Fast Exit 513 WR=010 3 Clocks 514 DLL=0 Normal 515 TM=0 Normal 516 CL=011 CL=3 517 BT=0 sequential burst type 518 BL=010 burst length of 4 519 520 Mode Register 1: 0000 0100 0000 0000 : 0x0440 GAS LISTING /tmp/ccxobHen.s page 11 521 OUT=0 full strength 522 RDQS=0 Disable 523 DQS=1 Disable 524 OCD=000 Not supported 525 RTT=10 150 Ohm termination needed with two ranks populated 526 AL=00 0 527 ODS=0 100% 528 DLL=0 Normal/Enable 529 530 Mode Register 2: 0x0000 531 Mode Register 3: 0x0000 532 533 #define MEM_SDMODE0_DDR2 0x01272224 534 #define MEM_SDMODE1_DDR2 0x01272224 535 #define MEM_SDADDR0_DDR2 0x231003E0 536 #define MEM_SDADDR1_DDR2 0x00000000//0x231083E0 537 #define MEM_SDCONFIGA_DDR2 0x1140060A//0x3140060A 538 #define MEM_SDCONFIGB_DDR2 0xA012610C 539 #define MEM_MR0_DDR2 0x00000432 540 #define MEM_MR1_DDR2 0x40000440 541 #define MEM_MR2_DDR2 0x80000000 542 #define MEM_MR3_DDR2 0xC0000000 543 */ 544 545 #define MEM_400NS (396 * 4 / 10) 546 #define MEM_1MS (396 * 1000) 547 548 549 /********************************************************************/ 550 /********************************************************************/ 551 /********************************************************************/ 552 /********************************************************************/ 553 554 .text 555 .set noreorder 556 .set mips32 557 558 /* 559 * Step 1) Establish CPU endian mode. 560 * Little Endian 561 */ 562 0008 90B1083C li t0, AU1200_SYS_ADDR 563 000c 01000924 li t1, 1 564 0010 380009AD sw t1, sys_endian(t0) 565 0014 0F000000 sync 566 0018 00800A40 mfc0 t2, CP0_Config 567 001c 00808A40 mtc0 t2, CP0_Config 568 0020 00000000 nop 569 0024 00000000 nop 570 571 /* 572 * Step 2) Establish Status Register 573 * (set BEV, clear ERL, clear EXL, clear IE) 574 */ 575 0028 4000093C li t1, 0x00400000 576 002c 00608940 mtc0 t1, CP0_Status 577 ⌨️ 快捷键说明
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