reset_db1200.s

au1200下的boot代码

	 * (set OD, set K0=3)
	 */
	li	t1, 0x00080003
	mtc0	t1, CP0_Config0

	/*
	 * Step 4) Disable Watchpoint facilities
	 */
	li	t1, 0x00000000
	mtc0	t1, CP0_WatchLo
	mtc0	t1, CP0_IWatchLo

	/*
	 * Step 5) Disable the performance counters
	 */
	mtc0	zero, CP0_PerfCtrl
	nop

	/*
	 * Step 6) Establish EJTAG Debug register
	 */
	mtc0	zero, CP0_Debug
	nop

	/*
	 * Step 7) Establish Cause
	 * (set IV bit)
	 */
	li	t1, 0x00800000
	mtc0	t1, CP0_Cause

	/*
	 * Step 8) Initialize the caches
	 */
	li	t0, (16*1024)
	li	t1, 32
	li	t2, 0x80000000
	addu	t3, t0, t2
cacheloop:
	cache	0, 0(t2)
	cache	1, 0(t2)
	addu	t2, t1
	bne	t2, t3, cacheloop
	nop

	/* Run from cacheable space now */
	bal	cachehere
	nop
cachehere:
	li	t1, ~0x20000000 /* convert to KSEG0 */
	and	t0, ra, t1
	addi	t0, 5*4			/* 5 insns beyond cachehere */
	jr	t0
	nop

	/*
	 * Step 9) Initialize the TLB
	 */
	li	t0, 0		 	# index value
	li	t1, 0x00000000 	# entryhi value
	li	t2, 32		   	# 32 entries
tlbloop:
	/* Probe TLB for matching EntryHi */
	mtc0	t1, CP0_EntryHi
	tlbp
	nop

	/* Examine Index[P], 1=no matching entry */
	mfc0	t3, CP0_Index
	li	t4, 0x80000000
	and	t3, t4, t3
	addiu	t1, t1, 1		# increment t1 (asid)
	beq	zero, t3, tlbloop
	nop

	/* Initialize the TLB entry */
	mtc0	t0, CP0_Index
	mtc0	zero, CP0_EntryLo0
	mtc0	zero, CP0_EntryLo1
	mtc0	zero, CP0_PageMask
	tlbwi

	/* Do it again */
	addiu	t0, t0, 1	
	bne	t0, t2, tlbloop
	nop

	/* Establish Wired (and Random) */
	mtc0	zero, CP0_Wired
	nop

	/*
	 * Step 10) Establish CPU PLL frequency
	 */
	li	t0, AU1200_SYS_ADDR
	li	t1, SYS_CPUPLL
	sw	t1, sys_cpupll(t0)
	sync
	nop
	nop

	/*
	 * Step 11) Establish system bus divider
	 */
	li	t1, SYS_POWERCTRL
	sw	t1, sys_powerctrl(t0)
	sync

	/*
	 * Step 12) Establish AUX PLL frequency
	 */
	li	t0, AU1200_SYS_ADDR
	li	t1, SYS_AUXPLL
	sw	t1, sys_auxpll(t0)
	sync

	/*
	 * Step 13) Start the 32kHz oscillator
	 */
	li	t1, 0x00000100
	sw	t1, sys_cntctrl(t0)
	sync

	/*
	 * Step 14) Initialize static memory controller
	 */
	li	t0, AU1200_MEM_ADDR
	li	t1, MEM_STCFG0
	li	t2, MEM_STTIME0
	li	t3, MEM_STADDR0
	sw	t1, mem_stcfg0(t0)
	sw	t2, mem_sttime0(t0)
	sw	t3, mem_staddr0(t0)
	sync

	/* RCE1 */
	li	t1, MEM_STCFG1
	li	t2, MEM_STTIME1
	li	t3, MEM_STADDR1
	sw	t1, mem_stcfg1(t0)
	sw	t2, mem_sttime1(t0)
	sw	t3, mem_staddr1(t0)

	/* RCE2 */
	li	t1, MEM_STCFG2
	li	t2, MEM_STTIME2
	li	t3, MEM_STADDR2
	sw	t1, mem_stcfg2(t0)
	sw	t2, mem_sttime2(t0)
	sw	t3, mem_staddr2(t0)

	/* RCE3 */
	li	t1, MEM_STCFG3
	li	t2, MEM_STTIME3
	li	t3, MEM_STADDR3
	sw	t1, mem_stcfg3(t0)
	sw	t2, mem_sttime3(t0)
	sw	t3, mem_staddr3(t0)

	/* Address latch time */
	li	t1, MEM_STALTIME
	sw	t1, mem_staltime(t0)
	sync

	/* NAND */
	sw	zero, mem_stndctrl(t0)
	sync

	/*
	 * Step 15) Set peripherals to a known state
	 */
	li	t0, AU1200_IC0_ADDR
	li	t1, 0xFFFFFFFF
	sw	t1, ic_cfg0clr(t0)
	sw	t1, ic_cfg1clr(t0)
	sw	t1, ic_cfg2clr(t0)
	sw	t1, ic_srcset(t0)
	sw	t1, ic_assignset(t0)
	sw	t1, ic_wakeclr(t0)
	sw	t1, ic_maskclr(t0)
	sw	t1, ic_risingclr(t0)
	sw	t1, ic_fallingclr(t0)
	sw	zero, ic_testbit(t0)
	sync

	li	t0, AU1200_IC1_ADDR
	li	t1, 0xFFFFFFFF
	sw	t1, ic_cfg0clr(t0)
	sw	t1, ic_cfg1clr(t0)
	sw	t1, ic_cfg2clr(t0)
	sw	t1, ic_srcset(t0)
	sw	t1, ic_assignset(t0)
	sw	t1, ic_wakeclr(t0)
	sw	t1, ic_maskclr(t0)
	sw	t1, ic_risingclr(t0)
	sw	t1, ic_fallingclr(t0)
	sw	zero, ic_testbit(t0)
	sync

	li	t0, AU1200_SYS_ADDR
	sw	zero, sys_freqctrl0(t0)
	sw	zero, sys_freqctrl1(t0)
	sw	zero, sys_clksrc(t0)
	li	t1, 0x007E303F
	sw	t1, sys_pinfunc(t0)
	li	t1, 0xFFFFFFFF
	sw	t1, sys_trioutclr(t0)
	sw	zero, sys_pininputen(t0)
	sync

	li	t0, AU1200_GPIO2_ADDR
	li	t1,2
	sw	t1,gpio2_enable(t0)

	li	t0, AU1200_DDMA_ADDR
	sw	zero, ddma_inten(t0)

  	li	t0, AU1200_UART0_ADDR
	sw	zero, uart_enable(t0)

	li	t0, AU1200_UART1_ADDR
	sw	zero, uart_enable(t0)

	li	t0, AU1200_PSC0_ADDR
	sw	zero, psc_enable(t0)

	li	t0, AU1200_PSC1_ADDR
	sw	zero, psc_enable(t0)

	li	t0, AU1200_USB_ADDR
	li	t1, 0x00D02000
	sw	t1, usb_cfg(t0)

	li	t0, AU1200_LCD_ADDR
	sw	zero, lcd_screen(t0)

	li	t0, AU1200_SD0_ADDR
	sw	zero, sd_enable(t0)

	li	t0, AU1200_SD1_ADDR
	sw	zero, sd_enable(t0)

	li	t0, AU1200_SWC_ADDR
	sw	zero, swcnt_control(t0)

	li	t0, AU1200_AES_ADDR
	sw	zero, aes_status(t0)

	li	t0, AU1200_CIM_ADDR
	sw	zero, cim_enable(t0)
	sync


	/*
	 * Step 16) Determine cause of reset
	 */
	/* wait 10mS to debounce external signals */
	li	t1, MEM_1MS*10
1:	addi	t1, t1, -1
	bne	t1, zero, 1b
	nop

	li	t0, AU1200_SYS_ADDR
	lw	t1, sys_wakesrc(t0)

	/* Clear sys_wakemsk to prevent false events */
	sw	zero, sys_wakemsk(t0)
	sync

	/* Clear sys_wakesrc */
	//sw	zero, sys_wakesrc(t0)
	//sync

	/* Check for Hibernate Reset first */
	andi	t2, t1, 0x04
	bne	zero, t2, hibernatereset
	nop

	/* Check for Hardware Reset */
	andi	t2, t1, 0x01
	bne	zero, t2, hardwarereset
	nop

	/* Check for Sleep Wakeup */
	andi	t2, t1, 0x02
	bne	zero, t2, sleepwakeup
	nop

	/* Assume run-time reset */
	b	runtimereset
	nop


/************************************************************************/

hardwarereset:
runtimereset:
hibernatereset:
	/*
	 * Step 1) Initialize DRAM
	 * Step 2) Initialize board
	 * Step 3) Invoke application
	 */
	bal 	initDRAM
	nop 
   	bal	initBOARD
	nop
	b	alldone
	nop	 

sleepwakeup:
	/*
	 * Step 1) Wakeup DRAM
	 * Step 2) Initialize board
	 * Step 3) Resume application
	 */
  	bal	wakeupDRAM	
  	nop
	bal	initBOARD
	nop
	la	t0, AU1200_SYS_ADDR
	lw	sp, sys_scratch0(t0)
	lw	ra, sys_scratch1(t0)
	jr	ra
	nop

/*************************************************************************/

initDRAM:

	/* Only perform DRAM init if running from ROM/Flash */
	addu	t2, ra, zero	/* preserve ra */
	b	getPC
 	nop

getPC:
	lui	t0, 0x1F00      /* ROM/flash address? */
	and	t1, t0, ra
	addu	ra, t2, zero	/* restore ra */
	bne	t0, t1, initDDRdone
	nop

	/* wait 1mS before setup */
	li	t1, MEM_1MS
1:	addi	t1, t1, -1
	bne	t1, zero, 1b
	nop

initDDR2:
	li	t1, MEM_SDCONFIGA_DDR2
	li	t2, MEM_SDCONFIGB_DDR2
	li	t3, MEM_SDMODE0_DDR2
	li	t4, MEM_SDMODE1_DDR2
	li	v0, MEM_MR0_DDR2
	li	v1, MEM_MR1_DDR2
	li	t5, MEM_SDADDR0_DDR2
	li	t6, MEM_SDADDR1_DDR2
	li	a2, MEM_MR2_DDR2
	li	a3, MEM_MR3_DDR2

	li	t0, AU1200_MEM_ADDR
	or	t2, MEM_SDCONFIGB_BB /* block LCD/MAE during init */
	sw	t1, mem_sdconfiga(t0)
	sync
	sw	t2, mem_sdconfigb(t0)
	sync
	sw	t3, mem_sdmode0(t0)
	sw	t4, mem_sdmode1(t0)
	sw	t5, mem_sdaddr0(t0)
	sw	t6, mem_sdaddr1(t0)
	sync

	/*
	 * Initialization per Micron data sheet, page 72:
	 * 0. Power sequence
	 * 1. 200us delay
	 * 2. NOP w/ CKE
	 * 3. 400ns delay
	 * 4. PRECHARGE ALL
	 * 5. EMRS(3), EMRS(2)
	 * 6. EMRS(1) (DLL enable, OCD)
	 * 7. EMRS (DLL reset activated)
	 * 8. 200 clocks of idle
	 * 9. PRECHARGE ALL
	 * 10. AUTO REFRESH x 2
	 * 11. EMRS (DLL reset de-activated)
	 * Devices are now ready for use.
	 */

	/* NOP w/ CKE */
	lw	t1, mem_sdconfigb(t0)
	li	t2, MEM_SDCONFIGB_BA
	or	t1, t2, t1
	sw	t1, mem_sdconfigb(t0)
	sync

	/* wait 400nS */
	li	t1, MEM_400NS
2:	addi	t1, t1, -1
	bne	t1, zero, 2b
	nop

	/* PRECHARGE ALL */
	sw	zero, mem_sdprecmd(t0)
	sync

	/* LOAD MODE REGISTER extended mode register 3 */
	sw	a3, mem_sdwrmd0(t0)		
	sync
	sw	a3, mem_sdwrmd1(t0)		
	sync

	/* LOAD MODE REGISTER extended mode register 2 */
	sw	a2, mem_sdwrmd0(t0)		
	sync
	sw	a2, mem_sdwrmd1(t0)		
	sync

	/* LOAD MODE REGISTER extended mode register 1 */
	sw	v1, mem_sdwrmd0(t0)		
	sync
	sw	v1, mem_sdwrmd0(t0)		
	sync

	/* LOAD MODE REGISTER normal mode register DLL reset */
#define MR0_DLL 0x0100
	ori	t1, v0, MR0_DLL
	sw	t1, mem_sdwrmd0(t0)
	sync
	sw	t1, mem_sdwrmd1(t0)
	sync

	/* 200 clocks of idle */
	lw	t1, mem_sdconfigb(t0)
	li	t2, MEM_SDCONFIGB_BA
	or	t1, t2, t1
	sw	t1, mem_sdconfigb(t0)
	sync

	/* PRECHARGE ALL */
	sw	zero, mem_sdprecmd(t0)
	sync

	/* AUTO REFRESH x 2 */
	sw	zero, mem_sdautoref(t0)
	sync
	sw	zero, mem_sdautoref(t0)
	sync

	/* LOAD MODE REGISTER normal mode register */
	sw	v0, mem_sdwrmd0(t0)
	sync
	sw	v0, mem_sdwrmd1(t0)
	sync

	/* LOAD MODE REGISTER extended mode register 1 */
#define MR1_OCD_DEFAULT 0x0380
	ori	t1, v1, MR1_OCD_DEFAULT
	sw	t1, mem_sdwrmd0(t0)
	sync
	sw	t1, mem_sdwrmd1(t0)
	sync
	sw	v1, mem_sdwrmd0(t0)
	sync
	sw	v1, mem_sdwrmd1(t0)
	sync

initDDRdone:
	/* Enable refresh */
	li	t0, AU1200_MEM_ADDR
	lw	t1, mem_sdconfiga(t0)
	li	t2, MEM_SDCONFIGA_E
	or	t1, t2, t1
	sw	t1, mem_sdconfiga(t0)
	sync

	/* Allow MAE/LCD */
	lw	t1, mem_sdconfigb(t0)
	li	t2, ~MEM_SDCONFIGB_BB
	and	t1, t2, t1
	sw	t1, mem_sdconfigb(t0)
	sync

	/* wait 1mS after setup */
	li	t1, MEM_1MS
1:	addi	t1, t1, -1
	bne	t1, zero, 1b
	nop

	jr		ra
	nop


/********************************************************************/

wakeupDRAM:	

	li	t1, MEM_SDCONFIGA_DDR2
	li	t2, MEM_SDCONFIGB_DDR2
	li	t3, MEM_SDMODE0_DDR2
	li	t4, MEM_SDMODE1_DDR2
	li	t5, MEM_SDADDR0_DDR2
	li	t6, MEM_SDADDR1_DDR2

	li	t0, AU1200_MEM_ADDR
	sw	t1, mem_sdconfiga(t0)
	sync
	sw	t2, mem_sdconfigb(t0)
	sync
	sw	t3, mem_sdmode0(t0)
	sw	t4, mem_sdmode1(t0)
	sw	t5, mem_sdaddr0(t0)
	sw	t6, mem_sdaddr1(t0)
	sync

	/* Assert DCKE - bring DDR out of self refresh */
	/* Note that two mem_sdsref are needed since state lost during sleep 		*/
	sw	zero, mem_sdsref(t0)
	sw	zero, mem_sdsref(t0)

	/*
	 * Issue 80ns of NOPs
	 */ 
	lw	t1, mem_sdconfigb(t0)
	li	t2, MEM_SDCONFIGB_BA
	or	t1, t2, t1
 	sw	t1, mem_sdconfigb(t0)
	sync 

	/*
	 * Perform burst refresh of 8K rows
	 */
	li	t1, 8192
burstrefresh:
	sw	zero, mem_sdautoref(t0)
	bne	zero, t1, burstrefresh
	addi	t1, t1, -1

	/* Enable refresh */
	lw	t1, mem_sdconfiga(t0)
	li	t2, MEM_SDCONFIGA_E
	or	t1, t2, t1
	sw	t1, mem_sdconfiga(t0)
	sync

 	jr	ra
	nop

/********************************************************************/

initBOARD:

	/*
	 * External and/or board-specific peripheral initialization
	 */

	/* Take IDE/LAN/DC/CIM out of reset */
/*
	li	t0, DB1200_BCSR_ADDR
	lh	t1, bcsr_resets(t0)
	ori	t1, 0x000F
	sh	t1, bcsr_resets(t0)
	sync
*/
	jr	ra
	nop

/********************************************************************/

alldone:

	/*
	 * Prepare to invoke application main()
	 */
	 .set reorder

/********************************************************************/