a2d.tan.rpt

ad取样

; N/A           ; None        ; -1.496 ns ; int       ; t_int[3]  ; clk      ;
; N/A           ; None        ; -1.539 ns ; int       ; t_int[1]  ; clk      ;
; N/A           ; None        ; -2.235 ns ; rst       ; t_int[1]  ; clk      ;
; N/A           ; None        ; -2.602 ns ; rst       ; t_int[0]  ; clk      ;
; N/A           ; None        ; -2.602 ns ; rst       ; t_int[2]  ; clk      ;
; N/A           ; None        ; -2.602 ns ; rst       ; t_int[3]  ; clk      ;
+---------------+-------------+-----------+-----------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun Apr 20 22:02:06 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off a2d -c a2d
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 120.03 MHz between source register "count[1]" and destination register "t_data[0]" (period= 8.331 ns)
    Info: + Longest register to register delay is 7.622 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y8_N6; Fanout = 6; REG Node = 'count[1]'
        Info: 2: + IC(2.063 ns) + CELL(0.740 ns) = 2.803 ns; Loc. = LC_X4_Y7_N5; Fanout = 1; COMB Node = 'LessThan0~116'
        Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 3.308 ns; Loc. = LC_X4_Y7_N6; Fanout = 3; COMB Node = 'LessThan0~117'
        Info: 4: + IC(0.790 ns) + CELL(0.511 ns) = 4.609 ns; Loc. = LC_X4_Y7_N4; Fanout = 8; COMB Node = 't_data[0]~344'
        Info: 5: + IC(1.770 ns) + CELL(1.243 ns) = 7.622 ns; Loc. = LC_X3_Y9_N5; Fanout = 1; REG Node = 't_data[0]'
        Info: Total cell delay = 2.694 ns ( 35.35 % )
        Info: Total interconnect delay = 4.928 ns ( 64.65 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.819 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 22; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X3_Y9_N5; Fanout = 1; REG Node = 't_data[0]'
            Info: Total cell delay = 2.081 ns ( 54.49 % )
            Info: Total interconnect delay = 1.738 ns ( 45.51 % )
        Info: - Longest clock path from clock "clk" to source register is 3.819 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 22; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X5_Y8_N6; Fanout = 6; REG Node = 'count[1]'
            Info: Total cell delay = 2.081 ns ( 54.49 % )
            Info: Total interconnect delay = 1.738 ns ( 45.51 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tsu for register "t_int[0]" (data pin = "rst", clock pin = "clk") is 3.156 ns
    Info: + Longest pin to register delay is 6.642 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 19; PIN Node = 'rst'
        Info: 2: + IC(2.440 ns) + CELL(0.740 ns) = 4.343 ns; Loc. = LC_X4_Y7_N9; Fanout = 4; COMB Node = 't_int[0]~321'
        Info: 3: + IC(1.056 ns) + CELL(1.243 ns) = 6.642 ns; Loc. = LC_X5_Y7_N8; Fanout = 5; REG Node = 't_int[0]'
        Info: Total cell delay = 3.146 ns ( 47.37 % )
        Info: Total interconnect delay = 3.496 ns ( 52.63 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 22; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X5_Y7_N8; Fanout = 5; REG Node = 't_int[0]'
        Info: Total cell delay = 2.081 ns ( 54.49 % )
        Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: tco from clock "clk" to destination pin "ld[2]" through register "t_data[2]" is 11.673 ns
    Info: + Longest clock path from clock "clk" to source register is 3.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 22; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X3_Y9_N3; Fanout = 1; REG Node = 't_data[2]'
        Info: Total cell delay = 2.081 ns ( 54.49 % )
        Info: Total interconnect delay = 1.738 ns ( 45.51 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 7.478 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y9_N3; Fanout = 1; REG Node = 't_data[2]'
        Info: 2: + IC(5.156 ns) + CELL(2.322 ns) = 7.478 ns; Loc. = PIN_78; Fanout = 0; PIN Node = 'ld[2]'
        Info: Total cell delay = 2.322 ns ( 31.05 % )
        Info: Total interconnect delay = 5.156 ns ( 68.95 % )
Info: th for register "t_data[4]" (data pin = "datain[4]", clock pin = "clk") is -1.040 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 22; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X3_Y9_N2; Fanout = 1; REG Node = 't_data[4]'
        Info: Total cell delay = 2.081 ns ( 54.49 % )
        Info: Total interconnect delay = 1.738 ns ( 45.51 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 5.080 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_5; Fanout = 1; PIN Node = 'datain[4]'
        Info: 2: + IC(3.668 ns) + CELL(0.280 ns) = 5.080 ns; Loc. = LC_X3_Y9_N2; Fanout = 1; REG Node = 't_data[4]'
        Info: Total cell delay = 1.412 ns ( 27.80 % )
        Info: Total interconnect delay = 3.668 ns ( 72.20 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 100 megabytes of memory during processing
    Info: Processing ended: Sun Apr 20 22:02:07 2008
    Info: Elapsed time: 00:00:01