a2d.tan.qmsg

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{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 7 -1 0 } } { "e:/install files/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/install files/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[1\] register t_data\[0\] 120.03 MHz 8.331 ns Internal " "Info: Clock \"clk\" has Internal fmax of 120.03 MHz between source register \"count\[1\]\" and destination register \"t_data\[0\]\" (period= 8.331 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.622 ns + Longest register register " "Info: + Longest register to register delay is 7.622 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LC_X5_Y8_N6 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y8_N6; Fanout = 6; REG Node = 'count\[1\]'" {  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[1] } "NODE_NAME" } } { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.063 ns) + CELL(0.740 ns) 2.803 ns LessThan0~116 2 COMB LC_X4_Y7_N5 1 " "Info: 2: + IC(2.063 ns) + CELL(0.740 ns) = 2.803 ns; Loc. = LC_X4_Y7_N5; Fanout = 1; COMB Node = 'LessThan0~116'" {  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.803 ns" { count[1] LessThan0~116 } "NODE_NAME" } } { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 3.308 ns LessThan0~117 3 COMB LC_X4_Y7_N6 3 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 3.308 ns; Loc. = LC_X4_Y7_N6; Fanout = 3; COMB Node = 'LessThan0~117'" {  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { LessThan0~116 LessThan0~117 } "NODE_NAME" } } { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.790 ns) + CELL(0.511 ns) 4.609 ns t_data\[0\]~344 4 COMB LC_X4_Y7_N4 8 " "Info: 4: + IC(0.790 ns) + CELL(0.511 ns) = 4.609 ns; Loc. = LC_X4_Y7_N4; Fanout = 8; COMB Node = 't_data\[0\]~344'" {  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.301 ns" { LessThan0~117 t_data[0]~344 } "NODE_NAME" } } { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.770 ns) + CELL(1.243 ns) 7.622 ns t_data\[0\] 5 REG LC_X3_Y9_N5 1 " "Info: 5: + IC(1.770 ns) + CELL(1.243 ns) = 7.622 ns; Loc. = LC_X3_Y9_N5; Fanout = 1; REG Node = 't_data\[0\]'" {  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.013 ns" { t_data[0]~344 t_data[0] } "NODE_NAME" } } { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.694 ns ( 35.35 % ) " "Info: Total cell delay = 2.694 ns ( 35.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.928 ns ( 64.65 % ) " "Info: Total interconnect delay = 4.928 ns ( 64.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.622 ns" { count[1] LessThan0~116 LessThan0~117 t_data[0]~344 t_data[0] } "NODE_NAME" } } { "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "7.622 ns" { count[1] LessThan0~116 LessThan0~117 t_data[0]~344 t_data[0] } { 0.000ns 2.063ns 0.305ns 0.790ns 1.770ns } { 0.000ns 0.740ns 0.200ns 0.511ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 22 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 22; CLK Node = 'clk'" {  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns t_data\[0\] 2 REG LC_X3_Y9_N5 1 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X3_Y9_N5; Fanout = 1; REG Node = 't_data\[0\]'" {  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk t_data[0] } "NODE_NAME" } } { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk t_data[0] } "NODE_NAME" } } { "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout t_data[0] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 22 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 22; CLK Node = 'clk'" {  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns count\[1\] 2 REG LC_X5_Y8_N6 6 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X5_Y8_N6; Fanout = 6; REG Node = 'count\[1\]'" {  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk count[1] } "NODE_NAME" } } { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk count[1] } "NODE_NAME" } } { "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout count[1] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk t_data[0] } "NODE_NAME" } } { "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout t_data[0] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk count[1] } "NODE_NAME" } } { "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout count[1] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.622 ns" { count[1] LessThan0~116 LessThan0~117 t_data[0]~344 t_data[0] } "NODE_NAME" } } { "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "7.622 ns" { count[1] LessThan0~116 LessThan0~117 t_data[0]~344 t_data[0] } { 0.000ns 2.063ns 0.305ns 0.790ns 1.770ns } { 0.000ns 0.740ns 0.200ns 0.511ns 1.243ns } "" } } { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk t_data[0] } "NODE_NAME" } } { "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout t_data[0] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk count[1] } "NODE_NAME" } } { "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout count[1] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "t_int\[0\] rst clk 3.156 ns register " "Info: tsu for register \"t_int\[0\]\" (data pin = \"rst\", clock pin = \"clk\") is 3.156 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.642 ns + Longest pin register " "Info: + Longest pin to register delay is 6.642 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns rst 1 PIN PIN_20 19 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 19; PIN Node = 'rst'" {  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.440 ns) + CELL(0.740 ns) 4.343 ns t_int\[0\]~321 2 COMB LC_X4_Y7_N9 4 " "Info: 2: + IC(2.440 ns) + CELL(0.740 ns) = 4.343 ns; Loc. = LC_X4_Y7_N9; Fanout = 4; COMB Node = 't_int\[0\]~321'" {  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.180 ns" { rst t_int[0]~321 } "NODE_NAME" } } { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.056 ns) + CELL(1.243 ns) 6.642 ns t_int\[0\] 3 REG LC_X5_Y7_N8 5 " "Info: 3: + IC(1.056 ns) + CELL(1.243 ns) = 6.642 ns; Loc. = LC_X5_Y7_N8; Fanout = 5; REG Node = 't_int\[0\]'" {  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.299 ns" { t_int[0]~321 t_int[0] } "NODE_NAME" } } { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.146 ns ( 47.37 % ) " "Info: Total cell delay = 3.146 ns ( 47.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.496 ns ( 52.63 % ) " "Info: Total interconnect delay = 3.496 ns ( 52.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.642 ns" { rst t_int[0]~321 t_int[0] } "NODE_NAME" } } { "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "6.642 ns" { rst rst~combout t_int[0]~321 t_int[0] } { 0.000ns 0.000ns 2.440ns 1.056ns } { 0.000ns 1.163ns 0.740ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 22 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 22; CLK Node = 'clk'" {  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns t_int\[0\] 2 REG LC_X5_Y7_N8 5 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X5_Y7_N8; Fanout = 5; REG Node = 't_int\[0\]'" {  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk t_int[0] } "NODE_NAME" } } { "a2d.vhd" "" { Text "E:/08design/works/a2d/a2d.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk t_int[0] } "NODE_NAME" } } { "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout t_int[0] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.642 ns" { rst t_int[0]~321 t_int[0] } "NODE_NAME" } } { "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "6.642 ns" { rst rst~combout t_int[0]~321 t_int[0] } { 0.000ns 0.000ns 2.440ns 1.056ns } { 0.000ns 1.163ns 0.740ns 1.243ns } "" } } { "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install files/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk t_int[0] } "NODE_NAME" } } { "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install files/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout t_int[0] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}