📄 mcf523x.cfg
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ResetHalt
Delay 200
Stop
; --------------------------- Set VBR to beginning of SRAM ------------------
; writecontrolreg 0x0801 0x20000000
; --------------------------- RAMBAR INIT -----------------------------------
; Set RAMBAR = 0x20000001
writecontrolreg 0x0C05 0x20000001
; --------------------------- FLASH INIT ------------------------------------
; 2MB FLASH on CS0 at 0x00000000
writemem.w 0x40000080 0x0000
writemem.l 0x40000084 0x001F0001
writemem.w 0x4000008A 0x1980
delay 100
; --------------------------- SDRAM INIT ------------------------------------
; 16MB SDRAM at 0x10000000
; Set PAR_SDRAM to allow SDRAM signals to be enabled
writemem.b 0x40100046 0x3F
; Set PAR_AD to allow 32-bit SDRAM if the exteranl boot device is 16-bits
writemem.b 0x40100040 0xE1
; 16 MB SDRAM
writemem.w 0x40000040 0x0446
writemem.l 0x40000048 0x10001300
writemem.l 0x4000004C 0x00FC0001
; Set IP in DACR and init precharge.
writemem.l 0x40000048 0x10001308
writemem.l 0x10000000 0xAA55AA55
; Wait a bit
delay 100
; Set RE in DACR
writemem.l 0x40000048 0x10009300
; Issue IMRS
writemem.l 0x40000048 0x10009340
writemem.l 0x10000400 0xAA55AA55
; Wait a bit more
delay 600
; --------------------------- WCR DISABLE------------------------------------
writemem.w 0x40140000 0x0000
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