mcf523x.mem

一个开源的Modbus协议栈

// Memory Configuration File
//
// Description:
//  A memory configuration file contains commands that define the legally 
//  accessible areas of memory for your specific board. Useful for example 
//  when the debugger tries to display the content of a "char *" variable, 
//  that has not yet been initialized.
//  In this case the debugger may try to read from a bogus address, which
//  could cause a bus error.
//
// Board:
//  Freescale M5235BCCKIT
//

//         Memory Map:
//         --------------------------------------------------------------------
range      0x00000000 0x001FFFFF 4 Read         // 2 Mbytes External Flash
range      0x10000000 0x10FFFFFF 1 ReadWrite    // 16 Mbyte SDRAM
reserved   0x11000000 0x1FFFFFFF
range      0x20000000 0x2000FFFF 1 ReadWrite    // 64 Kbytes Internal SRAM
reserved   0x20010000 0x3FFFFFFF
reserved   0x40200000 0xfFFFFFFF

//         Memory Mapped Registers (IPSBAR= 0x40000000):
//         -------------------------------------------------------------------

// System Control Module Registers
range      0x40000000 0x40000003 4 ReadWrite    // IPSBAR
reserved   0x40000004 0x4000000F
range      0x40000010 0x40000010 1 ReadWrite    // CRSR
range      0x40000011 0x40000011 1 ReadWrite    // CWCR
range      0x40000012 0x40000012 1 ReadWrite    // LPICR
range      0x40000013 0x40000013 1 ReadWrite    // CWSR
range      0x40000014 0x40000017 4 ReadWrite    // DMAREQC
reserved   0x40000018 0x4000001B
range      0x4000001C 0x4000001F 4 ReadWrite    // MPARK
range      0x40000020 0x40000020 1 ReadWrite    // MPR
reserved   0x40000021 0x40000023
range      0x40000024 0x40000024 1 ReadWrite    // PACR0
range      0x40000025 0x40000025 1 ReadWrite    // PACR1
range      0x40000026 0x40000026 1 ReadWrite    // PACR2
range      0x40000027 0x40000027 1 ReadWrite    // PACR3
range      0x40000028 0x40000028 1 ReadWrite    // PACR4
reserved   0x40000029 0x40000029
range      0x4000002A 0x4000002A 1 ReadWrite    // PACR5
range      0x4000002B 0x4000002B 1 ReadWrite    // PACR6
range      0x4000002C 0x4000002C 1 ReadWrite    // PACR7
reserved   0x4000002D 0x4000002D
range      0x4000002E 0x4000002E 1 ReadWrite    // PACR8
reserved   0x4000002F 0x4000002F
range      0x40000030 0x40000030 1 ReadWrite    // GPACR0
reserved   0x40000031 0x40000031
range      0x40000032 0x40000032 1 ReadWrite    // GPACR1
reserved   0x40000033 0x4000003F

// SDRAM Registers
range      0x40000040 0x40000041 2 ReadWrite    // DCR
reserved   0x40000042 0x40000047
range      0x40000048 0x4000004B 4 ReadWrite    // DACR0
range      0x4000004C 0x4000004F 4 ReadWrite    // DMR0
range      0x40000050 0x40000053 4 ReadWrite    // DACR1
range      0x40000054 0x40000057 4 ReadWrite    // DMR1
reserved   0x40000058 0x4000007F

// Chip Select Module Registers
range      0x40000080 0x40000081 2 ReadWrite    // CSAR0
reserved   0x40000082 0x40000083
range      0x40000084 0x40000087 4 ReadWrite    // CSMR0
reserved   0x40000088 0x40000089
range      0x4000008A 0x4000008B 2 ReadWrite    // CSCR0
range      0x4000008C 0x4000008D 2 ReadWrite    // CSAR1
reserved   0x4000008E 0x4000008F
range      0x40000090 0x40000093 4 ReadWrite    // CSMR1
reserved   0x40000094 0x40000095
range      0x40000096 0x40000097 2 ReadWrite    // CSCR1
range      0x40000098 0x40000099 2 ReadWrite    // CSAR2
reserved   0x4000009A 0x4000009B
range      0x4000009C 0x4000009F 4 ReadWrite    // CSMR2
reserved   0x400000A0 0x400000A1
range      0x400000A2 0x400000A3 2 ReadWrite    // CSCR2
range      0x400000A4 0x400000A5 2 ReadWrite    // CSAR3
reserved   0x400000A6 0x400000A7
range      0x400000A8 0x400000AB 4 ReadWrite    // CSMR3
reserved   0x400000AC 0x400000AD
range      0x400000AE 0x400000AF 2 ReadWrite    // CSCR3
range      0x400000B0 0x400000B1 2 ReadWrite    // CSAR4
reserved   0x400000B2 0x400000B3
range      0x400000B4 0x400000B7 4 ReadWrite    // CSMR4
reserved   0x400000B8 0x400000B9
range      0x400000BA 0x400000BB 2 ReadWrite    // CSCR4
range      0x400000BC 0x400000BD 2 ReadWrite    // CSAR5
reserved   0x400000BE 0x400000BF
range      0x400000C0 0x400000C3 4 ReadWrite    // CSMR5
reserved   0x400000C4 0x400000C5
range      0x400000C6 0x400000C7 2 ReadWrite    // CSCR5
range      0x400000C8 0x400000C9 2 ReadWrite    // CSAR6
reserved   0x400000CA 0x400000CB
range      0x400000CC 0x400000CF 4 ReadWrite    // CSMR6
reserved   0x400000D0 0x400000D1
range      0x400000D2 0x400000D3 2 ReadWrite    // CSCR6
range      0x400000D4 0x400000D5 2 ReadWrite    // CSAR7
reserved   0x400000D6 0x400000D7
range      0x400000D8 0x400000DB 4 ReadWrite    // CSMR7
reserved   0x400000DC 0x400000DD
range      0x400000DE 0x400000DF 2 ReadWrite    // CSCR7
reserved   0x400000E0 0x400000FF

// DMA Channel 0 Registers
range      0x40000100 0x40000103 4 ReadWrite    // SAR0
range      0x40000104 0x40000107 4 ReadWrite    // DAR0
range      0x40000108 0x40000108 1 ReadWrite    // DSR0
range      0x40000109 0x4000010B 1 ReadWrite    // BCR0
range      0x4000010C 0x4000010F 4 ReadWrite    // DCR0

// DMA Channel 1 Registers
range      0x40000110 0x40000113 4 ReadWrite    // SAR1
range      0x40000114 0x40000117 4 ReadWrite    // DAR1
range      0x40000118 0x40000118 1 ReadWrite    // DSR1
range      0x40000119 0x4000011B 1 ReadWrite    // BCR1
range      0x4000011C 0x4000011F 4 ReadWrite    // DCR1

// DMA Channel 2 Registers
range      0x40000120 0x40000123 4 ReadWrite    // SAR2
range      0x40000124 0x40000127 4 ReadWrite    // DAR2
range      0x40000128 0x40000128 1 ReadWrite    // DSR2
range      0x40000129 0x4000012B 1 ReadWrite    // BCR2
range      0x4000012C 0x4000012F 4 ReadWrite    // DCR2

// DMA Channel 3 Registers
range      0x40000130 0x40000133 4 ReadWrite    // SAR3
range      0x40000134 0x40000137 4 ReadWrite    // DAR3
range      0x40000138 0x40000138 1 ReadWrite    // DSR3
range      0x40000139 0x4000013B 1 ReadWrite    // BCR3
range      0x4000013C 0x4000013F 4 ReadWrite    // DCR3
reserved   0x40000140 0x400001FF

// UART0 Registers
range      0x40000200 0x40000200 1 ReadWrite    // UMR10 (ReadWrite) / UMR20 (ReadWrite)
reserved   0x40000201 0x40000203
range      0x40000204 0x40000204 1 ReadWrite    // USR0 (Read) / UCSR0 (Write)
reserved   0x40000205 0x40000207
range      0x40000208 0x40000208 1 Write        // UCR0
reserved   0x40000209 0x4000020B
range      0x4000020C 0x4000020C 1 ReadWrite    // URB0 (Read) / UTB0 (Write)
reserved   0x4000020D 0x4000020F
range      0x40000210 0x40000210 1 ReadWrite    // UIPCR0 (Read) / UACR0 (Write)
reserved   0x40000211 0x40000213
range      0x40000214 0x40000214 1 ReadWrite    // UISR0 (Read) / UIMR0 (Write)
reserved   0x40000215 0x40000217
range      0x40000218 0x40000218 1 Write        // UBG10
reserved   0x40000219 0x4000021B
range      0x4000021C 0x4000021C 1 Write        // UBG20
reserved   0x4000021D 0x40000233
range      0x40000234 0x40000234 1 Read         // UIP0
reserved   0x40000235 0x40000237
range      0x40000238 0x40000238 1 Write        // UOP10
reserved   0x40000239 0x4000023B
range      0x4000023C 0x4000023C 1 Write        // UOP00
reserved   0x4000023D 0x4000023F

// UART1 Registers
range      0x40000240 0x40000240 1 ReadWrite    // UMR11 (ReadWrite) / UMR21 (ReadWrite)
reserved   0x40000241 0x40000243
range      0x40000244 0x40000244 1 ReadWrite    // USR1 (Read) / UCSR1 (Write)
reserved   0x40000245 0x40000247
range      0x40000248 0x40000248 1 Write        // UCR1
reserved   0x40000249 0x4000024B
range      0x4000024C 0x4000024C 1 ReadWrite    // URB1 (Read) / UTB1 (Write)
reserved   0x4000024D 0x4000024F
range      0x40000250 0x40000250 1 ReadWrite    // UIPCR1 (Read) / UACR1 (Write)
reserved   0x40000251 0x40000253
range      0x40000254 0x40000254 1 ReadWrite    // UISR1 (Read) / UIMR1 (Write)
reserved   0x40000255 0x40000257
range      0x40000258 0x40000258 1 Write        // UBG11
reserved   0x40000259 0x4000025B
range      0x4000025C 0x4000025C 1 Write        // UBG21
reserved   0x4000025D 0x40000273
range      0x40000274 0x40000274 1 Read         // UIP1
reserved   0x40000275 0x40000277
range      0x40000278 0x40000278 1 Write        // UOP11
reserved   0x40000279 0x4000027B
range      0x4000027C 0x4000027C 1 Write        // UOP01
reserved   0x4000027D 0x4000027F

// UART2 Registers
range      0x40000280 0x40000280 1 ReadWrite    // UMR12 (ReadWrite) / UMR22 (ReadWrite)
reserved   0x40000281 0x40000283
range      0x40000284 0x40000284 1 ReadWrite    // USR2 (Read) / UCSR2 (Write)
reserved   0x40000285 0x40000287
range      0x40000288 0x40000288 1 Write        // UCR2
reserved   0x40000289 0x4000028B
range      0x4000028C 0x4000028C 1 ReadWrite    // URB2 (Read) / UTB2 (Write)
reserved   0x4000028D 0x4000028F
range      0x40000290 0x40000290 1 ReadWrite    // UIPCR2 (Read) / UACR2 (Write)
reserved   0x40000291 0x40000293
range      0x40000294 0x40000294 1 ReadWrite    // UISR2 (Read) / UIMR2 (Write)
reserved   0x40000295 0x40000297
range      0x40000298 0x40000298 1 Write        // UBG12
reserved   0x40000299 0x4000029B
range      0x4000029C 0x4000029C 1 Write        // UBG22
reserved   0x4000029D 0x400002B3
range      0x400002B4 0x400002B4 1 Read         // UIP2
reserved   0x400002B5 0x400002B7
range      0x400002B8 0x400002B8 1 Write        // UOP12
reserved   0x400002B9 0x400002BB
range      0x400002BC 0x400002BC 1 Write        // UOP02
reserved   0x400002BD 0x400002FF

// I2C Registers
range      0x40000300 0x40000300 1 ReadWrite    // I2ADR
reserved   0x40000301 0x40000303
range      0x40000304 0x40000304 1 ReadWrite    // I2FDR
reserved   0x40000305 0x40000307
range      0x40000308 0x40000308 1 ReadWrite    // I2CR
reserved   0x40000309 0x4000030B
range      0x4000030C 0x4000030C 1 ReadWrite    // I2SR
reserved   0x4000030D 0x4000030F
range      0x40000310 0x40000310 1 ReadWrite    // I2DR
reserved   0x40000311 0x4000033F

// Queued Serial Peripheral Interface Module Registers
range      0x40000340 0x40000341 2 ReadWrite    // QMR
reserved   0x40000342 0x40000343
range      0x40000344 0x40000345 2 ReadWrite    // QDLYR
reserved   0x40000346 0x40000347
range      0x40000348 0x40000349 2 ReadWrite    // QWR
reserved   0x4000034A 0x4000034B
range      0x4000034C 0x4000034D 2 ReadWrite    // QIR
reserved   0x4000034E 0x4000034F
range      0x40000350 0x40000351 2 ReadWrite    // QAR
reserved   0x40000352 0x40000353
range      0x40000354 0x40000355 2 ReadWrite    // QDR
reserved   0x40000356 0x400003FF

// DMA Timer 0 Registers
range      0x40000400 0x40000401 2 ReadWrite    // DTMR0
range      0x40000402 0x40000402 1 ReadWrite    // DTXMR0
range      0x40000403 0x40000403 1 ReadWrite    // DTER0
range      0x40000404 0x40000407 4 ReadWrite    // DTRR0
range      0x40000408 0x4000040B 4 ReadWrite    // DTCR0
range      0x4000040C 0x4000040F 4 ReadWrite    // DTCN0
reserved   0x40000410 0x4000043F

// DMA Timer 1 Registers
range      0x40000440 0x40000441 2 ReadWrite    // DTMR1
range      0x40000442 0x40000442 1 ReadWrite    // DTXMR1
range      0x40000443 0x40000443 1 ReadWrite    // DTER1
range      0x40000444 0x40000447 4 ReadWrite    // DTRR1
range      0x40000448 0x4000044B 4 ReadWrite    // DTCR1
range      0x4000044C 0x4000044F 4 ReadWrite    // DTCN1
reserved   0x40000450 0x4000047F

// DMA Timer 2 Registers
range      0x40000480 0x40000481 2 ReadWrite    // DTMR2
range      0x40000482 0x40000482 1 ReadWrite    // DTXMR2
range      0x40000483 0x40000483 1 ReadWrite    // DTER2
range      0x40000484 0x40000487 4 ReadWrite    // DTRR2
range      0x40000488 0x4000048B 4 ReadWrite    // DTCR2
range      0x4000048C 0x4000048F 4 ReadWrite    // DTCN2
reserved   0x40000490 0x400004BF

// DMA Timer 3 Registers
range      0x400004C0 0x400004C1 2 ReadWrite    // DTMR3
range      0x400004C2 0x400004C2 1 ReadWrite    // DTXMR3
range      0x400004C3 0x400004C3 1 ReadWrite    // DTER3
range      0x400004C4 0x400004C7 4 ReadWrite    // DTRR3
range      0x400004C8 0x400004CB 4 ReadWrite    // DTCR3
range      0x400004CC 0x400004CF 4 ReadWrite    // DTCN3
reserved   0x400004D0 0x40000BFF

// Interrupt Controller Registers 0
range      0x40000C00 0x40000C03 4 Read         // IPRH0
range      0x40000C04 0x40000C07 4 Read         // IPRL0
range      0x40000C08 0x40000C0B 4 ReadWrite    // IMRH0
range      0x40000C0C 0x40000C0F 4 ReadWrite    // IMRL0
range      0x40000C10 0x40000C13 4 ReadWrite    // INTFRCH0
range      0x40000C14 0x40000C17 4 Read         // INTFRCL0
range      0x40000C18 0x40000C18 1 Read         // IRLR0
range      0x40000C19 0x40000C19 1 Read         // IACKLPR0
reserved   0x40000C1A 0x40000C40
range      0x40000C41 0x40000C41 1 Read         // ICR001
range      0x40000C42 0x40000C42 1 Read         // ICR002
range      0x40000C43 0x40000C43 1 Read         // ICR003
range      0x40000C44 0x40000C44 1 Read         // ICR004
range      0x40000C45 0x40000C45 1 Read         // ICR005
range      0x40000C46 0x40000C46 1 Read         // ICR006
range      0x40000C47 0x40000C47 1 Read         // ICR007
range      0x40000C48 0x40000C48 1 ReadWrite    // ICR008
range      0x40000C49 0x40000C49 1 ReadWrite    // ICR009