📄 wrrc500.c
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return i;
}
///////////////////////////////////////////////////////////////////////
// M I F A R E C O M M O N R E Q U E S T
///////////////////////////////////////////////////////////////////////
char Mf500PiccCommonRequest(unsigned char req_code, unsigned char *atq)
{
char status; // = MI_OK;
char mylen;
//************* initialize ******************************
PcdSetTmo(106);
RegChannelRedundancy=0x03; // RxCRC and TxCRC disable, parity enable
RegControl = RegControl & (~0x08); // disable crypto 1 unit
RegBitFraming=0x07; // set TxLastBits to 7
RegTxControl = RegTxControl|0x03; //加
RegInterruptEn=0x3F; // disable all interrupts
RegInterruptRq=0x3F; // reset interrupt requests
// RegInterruptEn=0xBF;
RegCommand=0x00; //PCD_IDLE; // terminate probably running command
RegControl=RegControl | 0x01;//clear FIFO
RegFIFOData=req_code; //write request code
RegInterruptEn=0xA4; //enable TimerIRq and IdleIRq
RegCommand=PCD_TRANSCEIVE; //0x1e; //start command
MRC500_CNT=0x00;
// S_INT=1;
// while(S_INT);
while( (!(RegPrimaryStatus & 0x08)) && (MRC500_CNT<=20000) ) {MRC500_CNT+=1;} //wait for completion or timeout
if(MRC500_CNT>10000) // access mrc500 timeout
{
RegCommand=0x00; //PCD_IDLE; // terminate running command
status= MI_ACCESSTIMEOUT;
return status;
}
status=RegInterruptRq; //read interrupt request source
if( status & 0x20) status = MI_NOTAGERR; // timeout error
else
{
RegControl=RegControl | 0x04; // stop timer now
status=RegErrorFlag & 0x17;//read error flag
if(status)
{
// dv=2;
if (status & 0x01) status = MI_COLLERR; // collision detected
else if(status & 0x02) status = MI_PARITYERR; // parity error
else if(status & 0x04) status = MI_FRAMINGERR; // framing error
else status = MI_OVFLERR; // FIFO overflow
//else if(status & 0x08) status = MI_CRCERR; //CRC error
}
else
{
delay_1ms(1);
mylen=RegFIFOLength;
/*while(mylen!=0x02)
{
MRC500_CNT=0x00;
if(MRC500_CNT<10000) MRC500_CNT++;
mylen=RegFIFOLength;
}*/
if(RegFIFOLength==0x02) //received data length
{
*atq = RegFIFOData; //read atq
atq++;
*atq = RegFIFOData;
status=MI_OK;
}
else status=MI_BITCOUNTERR;
}
}
RegCommand=0x00; //PCD_IDLE; // terminate running command
return status;
}
///////////////////////////////////////////////////////////////////////
// M I F A R E C A S C A D E D S E L E C T
// for extended serial number
///////////////////////////////////////////////////////////////////////
char Mf500PiccCascSelect(unsigned char *snr)
{
char status;// = MI_OK;
PcdSetTmo(106);
RegChannelRedundancy=0x0F; // RxCRC,TxCRC, Parity enable
RegControl = RegControl & (~0x08); // disable crypto 1 unit
RegInterruptEn=0x7F; // disable all interrupts
RegInterruptRq=0x7F; // reset interrupt requests
RegCommand=0x00; //PCD_IDLE; // terminate probably running command
RegControl=RegControl | 0x01;//clear FIFO
RegFIFOData=0x93; //write code "SEL"
RegFIFOData=0x70; //write code "NVB"
for(status=0;status<4;status++) RegFIFOData= snr[status]; //write snr
status=snr[0]^snr[1]^snr[2]^snr[3]; //BCC
RegFIFOData=status; //write BCC
RegInterruptEn=0xA4; //enable TimerIRq and IdleIRq
RegCommand=PCD_TRANSCEIVE; //0x1e; //start command
MRC500_CNT=0x00;
while( (!(RegPrimaryStatus & 0x08)) && (MRC500_CNT<=20000) ) {MRC500_CNT+=1;} // wait for completion or timeout
if(MRC500_CNT>10000) // access mrc500 timeout
{
RegCommand=0x00; //PCD_IDLE; // terminate running command
status= MI_ACCESSTIMEOUT;
return status;
}
status=RegInterruptRq; //read interrupt request source
if( status & 0x20) status = MI_NOTAGERR; // timeout error
else
{
//====================================================
delay_1ms(1);
//====================================================
RegControl=RegControl | 0x04; // stop timer now
status=RegErrorFlag & 0x1F;//read error flag
if(status)
{
if (status & 0x01) status = MI_COLLERR; // collision detected
else if(status & 0x02) status = MI_PARITYERR; // parity error
else if(status & 0x04) status = MI_FRAMINGERR; // framing error
else if(status & 0x10) status = MI_OVFLERR; // FIFO overflow
else status = MI_CRCERR; //CRC error
}
else
{
if(RegFIFOLength==0x01) //received data length
{
//status = RegFIFOData & 0x04; //read SAK
if (RegFIFOData & 0x04) status = MI_SAKERR; //SAK error
else status=MI_OK;
}
else status=MI_BITCOUNTERR;
}
}
RegCommand=0x00; //PCD_IDLE; // terminate running command
return status;
}
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
// C O D E K E Y S
///////////////////////////////////////////////////////////////////////
void CodeKey( unsigned char *uncoded, // 6 bytes key value uncoded
unsigned char *coded) // 12 bytes key value coded
{
unsigned char xdata cnt = 0;
unsigned char xdata ln = 0; // low nibble
unsigned char xdata hn = 0; // high nibble
for (cnt = 0; cnt < 6; cnt++)
{
ln = uncoded[cnt] & 0x0F;
hn = uncoded[cnt] >> 4;
coded[cnt * 2 + 1] = (~ln << 4) | ln;
coded[cnt * 2 ] = (~hn << 4) | hn;
}
}
///////////////////////////////////////////////////////////////////////
// LOAD KEY TO MRC500 MASTER KEY BUFFER (WITH PROVIDED KEYS)
///////////////////////////////////////////////////////////////////////
char MRC500LoadKey1(unsigned char *keys) //6 bytes key value uncoded
{
char status;// = MI_OK;
unsigned char idata coded_keys[12];
CodeKey(keys,coded_keys); //code keys to 12 bytes
PcdSetTmo(106);
RegInterruptEn=0x7F; // disable all interrupts
RegInterruptRq=0x7F; // reset interrupt requests
RegCommand=0x00; //PCD_IDLE; // terminate probably running command
RegControl=RegControl | 0x01;//clear FIFO
for(status=0;status<12;status++) RegFIFOData=coded_keys[status]; //write 12bytes key to fifo
RegInterruptEn=0xA4; //enable TimerIRq and IdleIRq
RegCommand=PCD_LOADKEY; //0x19; //start command
MRC500_CNT=0x00; //reset u-controller timeout
while( (!(RegPrimaryStatus & 0x08)) && (MRC500_CNT<20000) ) {MRC500_CNT+=1;} // wait for completion or timeout
if(MRC500_CNT>10000) // access mrc500 timeout
{
RegCommand=0x00; //PCD_IDLE; // terminate running command
status= MI_ACCESSTIMEOUT;
return status;
}
status=RegInterruptRq; //read interrupt request source
if( status & 0x20) status = MI_NOTAGERR; // timeout error
else
{
RegControl=RegControl | 0x04; // stop timer now
status=RegErrorFlag;//read error flag
if(status)
{
if (status & 0x40) status = MI_KEYERR; // key error flag set
else status = MI_AUTHERR; // generic authentication error
}
else
{
status=MI_OK;
}
}
RegCommand=0x00; //PCD_IDLE; // terminate running command
return status;
}
///////////////////////////////////////////////////////////////////////
// A U T H E N T I C A T I O N
///////////////////////////////////////////////////////////////////////
char MRC500PiccAuthentication( unsigned char auth_mode, // PICC_AUTHENT1A or PICC_AUTHENT1B
unsigned char *snr, // 4 bytes card serial number
unsigned char block) // 0 <= block <= 64
{
char status; // = MI_OK;
PcdSetTmo(106);
RegInterruptEn=0x7F; // disable all interrupts
RegInterruptRq=0x7F; // reset interrupt requests
RegCommand=0x00; //PCD_IDLE; // terminate probably running command
RegControl=RegControl | 0x01;//clear FIFO
RegFIFOData=auth_mode; // write authentication command
RegFIFOData=block; // write block number for authentication
for(status=0;status<4;status++) RegFIFOData=snr[status]; //write snr
RegInterruptEn=0xA4;//0xA4; //enable TimerIRq and IdleIRq
RegCommand=PCD_AUTHENT1; //PCD_AUTHENT1; //start command
MRC500_CNT=0x00; //reset u-controller timeout
while( (!(RegPrimaryStatus & 0x08)) && (MRC500_CNT<20000) ) {MRC500_CNT+=1;} // wait for completion or timeout
if(MRC500_CNT>10000) // access mrc500 timeout
{
RegCommand=0x00; //PCD_IDLE; // terminate running command
status= MI_ACCESSTIMEOUT;
return status;
}
status=RegInterruptRq; //read interrupt request source
if( !(status & 0x04)) status= MI_NOTAGERR; // timeout error
else
{
delay_1ms(1);
if(RegSecondaryStatus & 0x07) status=MI_BITCOUNTERR; // RxLastBits mu⌨️ 快捷键说明
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