📄 wrrc500.lst
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183 1 while(MRC500_CNT <= 10000){MRC500_CNT+=1;} //About 20 ms
184 1
185 1 RegClockQControl = RegClockQControl & (~0x40);
186 1
187 1 // The following values for RegBitPhase and
188 1 // RegRxThreshold represents an optimal
189 1 // value for our demo package. For user
190 1 // implementation some changes could be
191 1 // necessary
192 1 // initialize bit phase
193 1 RegBitPhase=0xAD;
194 1
195 1 // initialize minlevel
196 1 RegRxThreshold=0xFF;
197 1 // disable auto power down
198 1 RegRxControl2=1;
199 1
200 1 // Depending on the processing speed of the
201 1 // operation environment, the waterlevel
202 1 // can be adapted. (not very critical for
203 1 // mifare applications)
204 1 // initialize waterlevel to value 4
205 1 RegFIFOLevel=0x1A; // initialize to 26d
206 1
207 1 //Timer Konfiguration
208 1 RegTimerControl=0x02; // TStopRxEnd=0,TStopRxBeg=0,
209 1 // TStartTxEnd=1,TStartTxBeg=0
210 1 // timer must be stopped manually
211 1
212 1 RegIRqPinConfig=0x3; // interrupt active low enable
213 1
214 1 PcdRfReset(1); // Rf - reset and enable output driver
215 1
216 1 }
217 //////////////////////////////////////////////////////////////////////
218 // RF R E S E T
219 ///////////////////////////////////////////////////////////////////////
220 void PcdRfReset(unsigned char ms)
221 {
222 1 RegTxControl = RegTxControl & (~0x03);
223 1 if (ms > 0)
224 1 {
225 2 MRC500_CNT=0;
226 2 while(MRC500_CNT <=10000){MRC500_CNT+=1;}
227 2 RegTxControl = RegTxControl | 0x03;
228 2 }
229 1 }
230
231 ///////////////////////////////////////////////////////////////////////
232 // S e t T i m e o u t L E N G T H
233 ///////////////////////////////////////////////////////////////////////
234 void PcdSetTmo(unsigned char tmoLength)
235 {
236 1 switch(tmoLength)
237 1 { // timer clock frequency 13,56 MHz
238 2 case 1: // short timeout (1,0 ms)
239 2 RegTimerClock=0x07; // TAutoRestart=0,TPrescale=128
240 2 RegTimerReload=0x6a;// TReloadVal = 'h6a =106(dec)
241 2 break;
C51 COMPILER V8.01 WRRC500 03/29/2008 15:10:44 PAGE 5
242 2 case 2: // medium timeout (1,5 ms)
243 2 RegTimerClock=0x07; // TAutoRestart=0,TPrescale=128
244 2 RegTimerReload=0xa0;// TReloadVal = 'ha0 =160(dec)
245 2 break;
246 2 case 3: // long timeout (6 ms)
247 2 RegTimerClock=0x09; // TAutoRestart=0,TPrescale=4*128
248 2 RegTimerReload=0xa0;// TReloadVal = 'ha0 =160(dec)
249 2 break;
250 2 case 4: // long timeout (9.6 ms)
251 2 RegTimerClock=0x09; // TAutoRestart=0,TPrescale=4*128
252 2 RegTimerReload=0xff;// TReloadVal = 'ff =255(dec)
253 2 break;
254 2 default: // short timeout (1,0 ms)
255 2 RegTimerClock=0x07; // TAutoRestart=0,TPrescale=128
256 2 RegTimerReload=tmoLength;// TReloadVal = tmoLength
257 2 break;
258 2 }
259 1 }
260 //-------------------------------------------------------------
261 char MCRReset_1(void)
262 {
263 1
264 1 char i;
265 1 while((RegCommand & 0x3F));
266 1 RegPage=0;//0x80;//WriteRawRC(RegPage,0x80); // Dummy access in order to determine the bus
267 1 // configuration
268 1 // necessary read access
269 1 // after first write access, the returned value
270 1 // should be zero ==> interface recognized
271 1
272 1 if (RegCommand != 0x00)//if (ReadRawRC(RegCommand) != 0x00)
273 1 {
274 2 i = MI_INTERFACEERR;
275 2 }
276 1 else
277 1 {
278 2 i = MI_OK; // sequence is ok
279 2 }
280 1 return i;
281 1 }
282 ///////////////////////////////////////////////////////////////////////
283 // M I F A R E C O M M O N R E Q U E S T
284 ///////////////////////////////////////////////////////////////////////
285 char Mf500PiccCommonRequest(unsigned char req_code, unsigned char *atq)
286 {
287 1 char status; // = MI_OK;
288 1 char mylen;
289 1
290 1 //************* initialize ******************************
291 1 PcdSetTmo(106);
292 1
293 1 RegChannelRedundancy=0x03; // RxCRC and TxCRC disable, parity enable
294 1 RegControl = RegControl & (~0x08); // disable crypto 1 unit
295 1 RegBitFraming=0x07; // set TxLastBits to 7
296 1 RegTxControl = RegTxControl|0x03; //加
297 1 RegInterruptEn=0x3F; // disable all interrupts
298 1 RegInterruptRq=0x3F; // reset interrupt requests
299 1 // RegInterruptEn=0xBF;
300 1 RegCommand=0x00; //PCD_IDLE; // terminate probably running command
301 1
302 1 RegControl=RegControl | 0x01;//clear FIFO
303 1
C51 COMPILER V8.01 WRRC500 03/29/2008 15:10:44 PAGE 6
304 1 RegFIFOData=req_code; //write request code
305 1
306 1 RegInterruptEn=0xA4; //enable TimerIRq and IdleIRq
307 1
308 1 RegCommand=PCD_TRANSCEIVE; //0x1e; //start command
309 1
310 1 MRC500_CNT=0x00;
311 1 // S_INT=1;
312 1 // while(S_INT);
313 1
314 1 while( (!(RegPrimaryStatus & 0x08)) && (MRC500_CNT<=20000) ) {MRC500_CNT+=1;} //wait for completion or t
-imeout
315 1
316 1 if(MRC500_CNT>10000) // access mrc500 timeout
317 1 {
318 2 RegCommand=0x00; //PCD_IDLE; // terminate running command
319 2 status= MI_ACCESSTIMEOUT;
320 2 return status;
321 2 }
322 1
323 1 status=RegInterruptRq; //read interrupt request source
324 1
325 1 if( status & 0x20) status = MI_NOTAGERR; // timeout error
326 1
327 1 else
328 1 {
329 2 RegControl=RegControl | 0x04; // stop timer now
330 2 status=RegErrorFlag & 0x17;//read error flag
331 2 if(status)
332 2 {
333 3 // dv=2;
334 3 if (status & 0x01) status = MI_COLLERR; // collision detected
335 3 else if(status & 0x02) status = MI_PARITYERR; // parity error
336 3 else if(status & 0x04) status = MI_FRAMINGERR; // framing error
337 3 else status = MI_OVFLERR; // FIFO overflow
338 3 //else if(status & 0x08) status = MI_CRCERR; //CRC error
339 3
340 3 }
341 2 else
342 2 {
343 3
344 3 delay_1ms(1);
345 3 mylen=RegFIFOLength;
346 3 /*while(mylen!=0x02)
347 3 {
348 3 MRC500_CNT=0x00;
349 3 if(MRC500_CNT<10000) MRC500_CNT++;
350 3 mylen=RegFIFOLength;
351 3 }*/
352 3
353 3 if(RegFIFOLength==0x02) //received data length
354 3 {
355 4 *atq = RegFIFOData; //read atq
356 4 atq++;
357 4 *atq = RegFIFOData;
358 4 status=MI_OK;
359 4 }
360 3 else status=MI_BITCOUNTERR;
361 3 }
362 2 }
363 1
364 1 RegCommand=0x00; //PCD_IDLE; // terminate running command
C51 COMPILER V8.01 WRRC500 03/29/2008 15:10:44 PAGE 7
365 1 return status;
366 1 }
367
368
369 ///////////////////////////////////////////////////////////////////////
370 // M I F A R E C A S C A D E D S E L E C T
371 // for extended serial number
372 ///////////////////////////////////////////////////////////////////////
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