📄 sci_ti1m.lst
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19 =1
20 =1 See book for copyright details and other information.
21 =1
22 =1 -*------------------------------------------------------------------*/
23 =1
24 =1 // ------ Public function prototypes -------------------------------
25 =1
26 =1 void Hardware_Delay_T0(const tWord);
27 =1
28 =1 /*------------------------------------------------------------------*-
29 =1 ---- END OF FILE -------------------------------------------------
30 =1 -*------------------------------------------------------------------*/
40 #include "TLight_A.h"
1 =1 /*------------------------------------------------------------------*-
2 =1
3 =1 TLight_A.H (v1.00)
4 =1
5 =1 ------------------------------------------------------------------
6 =1
7 =1 - See TLight_A.C for details.
8 =1
9 =1
10 =1 COPYRIGHT
11 =1 ---------
12 =1
13 =1 This code is from the book:
14 =1
15 =1 PATTERNS FOR TIME-TRIGGERED EMBEDDED SYSTEMS by Michael J. Pont
16 =1 [Pearson Education, 2001; ISBN: 0-201-33138-1].
17 =1
18 =1 This code is copyright (c) 2001 by Michael J. Pont.
19 =1
20 =1 See book for copyright details and other information.
21 =1
22 =1 -*------------------------------------------------------------------*/
23 =1
24 =1 // ------ Public data type declarations ----------------------------
25 =1
26 =1 // Possible system states
27 =1 typedef
28 =1 enum {RED, RED_AMBER, GREEN, AMBER, BULB_BLOWN} eLight_State;
29 =1
30 =1
31 =1 // ------ Public constants -----------------------------------------
32 =1
33 =1 #define MASTER 1
34 =1 #define SLAVE 0
35 =1
36 =1 // ------ Public function prototypes -------------------------------
37 =1
38 =1 void TRAFFIC_LIGHTS_Init(void);
39 =1 void TRAFFIC_LIGHTS_Update(void);
40 =1
41 =1 void TRAFFIC_LIGHTS_Display_Safe_Output(void);
42 =1
43 =1 /*------------------------------------------------------------------*-
44 =1 ---- END OF FILE -------------------------------------------------
45 =1 -*------------------------------------------------------------------*/
41
C51 COMPILER V6.10 SCI_TI1M 04/18/2001 16:49:11 PAGE 15
42 // ------ Public variable declarations -----------------------------
43
44 // The array of tasks (see Sch51.c)
45 extern sTask SCH_tasks_G[SCH_MAX_TASKS];
46
47 // The error code variable (see Sch51.c)
48 extern tByte Error_code_G;
49
50 /*------------------------------------------------------------------*-
51
52 SCI_TICK1_MASTER_Init_T2()
53
54 Scheduler initialisation function. Prepares scheduler data
55 structures and sets up timer interrupts at required rate.
56
57 You must call this function before using the scheduler.
58
59 -*------------------------------------------------------------------*/
60 void SCI_TICK1_MASTER_Init_T2(void)
61 {
62 1 tByte i;
63 1
64 1 // No interrupts (yet)
65 1 EA = 0;
66 1
67 1 // ------ Set up the scheduler ----------------------------------
68 1 // Sort out the tasks
69 1 for (i = 0; i < SCH_MAX_TASKS; i++)
70 1 {
71 2 SCH_Delete_Task(i);
72 2 }
73 1
74 1 // Reset the global error variable
75 1 // - SCH_Delete_Task() will generate an error code,
76 1 // (because the task array is empty)
77 1 Error_code_G = 0;
78 1
79 1 // ------ Set up Timer 2 (begin) --------------------------------
80 1 // Now set up Timer 2
81 1 // 16-bit timer function with automatic reload
82 1
83 1 // Crystal is assumed to be 12 MHz
84 1 // The Timer 2 resolution is 0.000001 seconds (1 祍)
85 1 // The required Timer 2 overflow is 0.001 seconds (1 ms)
86 1 // - this takes 1000 timer ticks
87 1 // Reload value is 65536 - 1000 = 64536 (dec) = 0xFC18
88 1
89 1 T2CON = 0x04; // load Timer 2 control register
90 1 T2MOD = 0x00; // load Timer 2 mode register
91 1
92 1 TH2 = 0xFC; // load timer 2 high byte
93 1 RCAP2H = 0xFC; // load timer 2 reload capture reg, high byte
94 1 TL2 = 0x18; // load timer 2 low byte
95 1 RCAP2L = 0x18; // load timer 2 reload capture reg, low byte
96 1
97 1 ET2 = 1; // Timer 2 interrupt is enabled
98 1
99 1 TR2 = 1; // Start Timer 2
100 1 // ------ Set up Timer 2 (end) ----------------------------------
101 1 }
102
103 /*------------------------------------------------------------------*-
C51 COMPILER V6.10 SCI_TI1M 04/18/2001 16:49:11 PAGE 16
104
105 SCI_TICK1_MASTER_Start()
106
107 Starts the scheduler, by enabling interrupts.
108
109 NOTE: Usually called after all regular tasks are added,
110 to keep the tasks synchronised.
111
112 NOTE: ONLY THE SCHEDULER INTERRUPT SHOULD BE ENABLED!!!
113
114 -*------------------------------------------------------------------*/
115 void SCI_TICK1_MASTER_Start(void)
116 {
117 1 // Try to place system in 'safe' state at start or after errors
118 1 SCI_TICK1_MASTER_Enter_Safe_State();
119 1
120 1 // Delay here to cause the slave to time out and reset
121 1 // Adjust this delay to match the timeout periods on the slaves
122 1 Hardware_Delay_T0(500);
123 1
124 1 // Now send first tick to start the slave
125 1 // (starts on falling edge)
126 1 Interrupt_output_pin = 1;
127 1 Hardware_Delay_T0(5);
128 1 Interrupt_output_pin = 0;
129 1 Hardware_Delay_T0(5);
130 1
131 1 Interrupt_output_pin = 1; // Ready for first tick
132 1
133 1 // Start the scheduler
134 1 EA = 1;
135 1 }
136
137 /*------------------------------------------------------------------*-
138
139 SCI_TICK1_MASTER_Update_T2
140
141 This is the scheduler ISR. It is called at a rate determined by
142 the timer settings in SCI_TICK1_MASTER_Init_T2(). This version is
143 triggered by Timer 2 interrupts: timer is automatically reloaded.
144
145 -*------------------------------------------------------------------*/
146 void SCI_TICK1_MASTER_Update_T2(void) interrupt INTERRUPT_Timer_2_Overflow
147 {
148 1 tByte Index;
149 1
150 1 TF2 = 0; // Must manually clear this.
151 1
152 1 // Send 'tick' message to the slave
153 1 Interrupt_output_pin = 0;
154 1
155 1 // NOTE: calculations are in *TICKS* (not milliseconds)
156 1 for (Index = 0; Index < SCH_MAX_TASKS; Index++)
157 1 {
158 2 // Check if there is a task at this location
159 2 if (SCH_tasks_G[Index].pTask)
160 2 {
161 3 if (SCH_tasks_G[Index].Delay == 0)
162 3 {
163 4 // The task is due to run
164 4 SCH_tasks_G[Index].RunMe += 1; // Increment the run flag
165 4
C51 COMPILER V6.10 SCI_TI1M 04/18/2001 16:49:11 PAGE 17
166 4 if (SCH_tasks_G[Index].Period)
167 4 {
168 5 // Schedule this regular task to run again
169 5 SCH_tasks_G[Index].Delay = SCH_tasks_G[Index].Period;
170 5 }
171 4 }
172 3 else
173 3 {
174 4 // Not yet ready to run: just decrement the delay
175 4 SCH_tasks_G[Index].Delay -= 1;
176 4 }
177 3 }
178 2 }
179 1
180 1 // Prepare for next tick
181 1 Interrupt_output_pin = 1;
182 1 }
183
184 /*------------------------------------------------------------------*-
185
186 SCI_TICK1_MASTER_Enter_Safe_State()
187
188 This is the state entered by the system when:
189 (1) The node is powered up or reset
190 (2) The slave node fails
191 (3) The network has an error
192 (4) Ack messages are delayed for any other reason
193
194 Try to ensure that the system is in a 'safe' state in these
195 circumstances.
196
197 -*------------------------------------------------------------------*/
198 void SCI_TICK1_MASTER_Enter_Safe_State(void) reentrant
199 {
200 1 // USER DEFINED - Edit as required
201 1
202 1 // Here we display a safe output
203 1 TRAFFIC_LIGHTS_Display_Safe_Output();
204 1 }
205
206 /*------------------------------------------------------------------*-
207 ---- END OF FILE -------------------------------------------------
208 -*------------------------------------------------------------------*/
C51 COMPILER V6.10 SCI_TI1M 04/18/2001 16:49:11 PAGE 18
ASSEMBLY LISTING OF GENERATED OBJECT CODE
; FUNCTION SCI_TICK1_MASTER_Init_T2 (BEGIN)
; SOURCE LINE # 60
; SOURCE LINE # 61
; SOURCE LINE # 65
0000 C2AF CLR EA
; SOURCE LINE # 69
0002 E4 CLR A
0003 F500 R MOV i,A
0005 ?C0001:
; SOURCE LINE # 70
; SOURCE LINE # 71
0005 AF00 R MOV R7,i
0007 120000 E LCALL _SCH_Delete_Task
; SOURCE LINE # 72
000A 0500 R INC i
000C E500 R MOV A,i
000E C3 CLR C
000F 9402 SUBB A,#02H
0011 40F2 JC ?C0001
0013 ?C0002:
; SOURCE LINE # 77
0013 E4 CLR A
0014 F500 E MOV Error_code_G,A
; SOURCE LINE # 89
0016 75C804 MOV T2CON,#04H
; SOURCE LINE # 90
0019 F5C9 MOV T2MOD,A
; SOURCE LINE # 92
001B 75CDFC MOV TH2,#0FCH
; SOURCE LINE # 93
001E 75CBFC MOV RCAP2H,#0FCH
; SOURCE LINE # 94
0021 75CC18 MOV TL2,#018H
; SOURCE LINE # 95
0024 75CA18 MOV RCAP2L,#018H
; SOURCE LINE # 97
0027 D2AD SETB ET2
; SOURCE LINE # 99
0029 D2CA SETB TR2
; SOURCE LINE # 101
002B 22 RET
; FUNCTION SCI_TICK1_MASTER_Init_T2 (END)
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