📄 seltime_dc.rpt
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-- Node name is '~775~4'
-- Equation name is '~775~4', location is LC043, type is buried.
-- synthesized logic cell
_LC043 = LCELL( _EQ017 $ GND);
_EQ017 = sec0 & sec2 & !sec3 & !sel0 & !sel1 & !sel2
# !sec1 & !sec2 & sec3 & !sel0 & !sel1 & !sel2
# min5 & min6 & sel0 & sel1 & !sel2
# min4 & min6 & sel0 & sel1 & !sel2
# min4 & min5 & sel0 & sel1 & !sel2;
-- Node name is '~775~5'
-- Equation name is '~775~5', location is LC048, type is buried.
-- synthesized logic cell
_LC048 = LCELL( _EQ018 $ GND);
_EQ018 = sec5 & sec6 & sel0 & !sel1 & !sel2
# sec4 & sec6 & sel0 & !sel1 & !sel2
# sec4 & sec5 & sel0 & !sel1 & !sel2;
-- Node name is '~784~1'
-- Equation name is '~784~1', location is LC038, type is buried.
-- synthesized logic cell
_LC038 = LCELL( _EQ019 $ VCC);
_EQ019 = !_LC051 & _X012 & _X013 & _X014;
_X012 = EXP( min4 & !min5 & !min6 & sel0 & sel1 & !sel2);
_X013 = EXP( sec4 & !sec5 & !sec6 & sel0 & !sel1 & !sel2);
_X014 = EXP( hour4 & !hour5 & sel0 & !sel1 & sel2);
-- Node name is '~784~2'
-- Equation name is '~784~2', location is LC051, type is buried.
-- synthesized logic cell
_LC051 = LCELL( _EQ020 $ GND);
_EQ020 = min0 & !min1 & !min2 & !min3 & min4 & !min5 & !min6 & sec0 &
!sec1 & !sec2 & !sec3 & sec4 & !sec5 & !sec6 & !sel2
# hour0 & !hour1 & !hour2 & !hour3 & hour4 & !hour5 & sec0 &
!sec1 & !sec2 & !sec3 & sec4 & !sec5 & !sec6 & !sel1
# min0 & !min1 & !min2 & !min3 & !sel0 & sel1 & !sel2
# hour0 & !hour1 & !hour2 & !hour3 & !sel0 & !sel1 & sel2
# sec0 & !sec1 & !sec2 & !sec3 & !sel0 & !sel1 & !sel2;
-- Node name is '~791~1'
-- Equation name is '~791~1', location is LC054, type is buried.
-- synthesized logic cell
_LC054 = LCELL( _EQ021 $ VCC);
_EQ021 = min3 & !sel0 & sel1 & !sel2
# hour3 & !sel0 & !sel1 & sel2
# sec3 & !sel0 & !sel1 & !sel2;
-- Node name is '~793~1'
-- Equation name is '~793~1', location is LC012, type is buried.
-- synthesized logic cell
_LC012 = LCELL( _EQ022 $ GND);
_EQ022 = !sec2 & !sel0 & !sel1 & !sel2
# !min6 & sel0 & sel1
# !sec6 & sel0 & !sel1
# !min2 & !sel0 & sel1
# sel2 & _X015;
_X015 = EXP( hour2 & !sel0 & !sel1);
-- Node name is '~795~1'
-- Equation name is '~795~1', location is LC053, type is buried.
-- synthesized logic cell
_LC053 = LCELL( _EQ023 $ _EQ024);
_EQ023 = min5 & sel0 & sel1 & !sel2 & _X016 & _X017
# hour5 & sel0 & !sel1 & sel2 & _X016 & _X017
# sec5 & sel0 & !sel1 & !sel2 & _X016 & _X017
# min1 & !sel0 & sel1 & !sel2 & _X016 & _X017;
_X016 = EXP( sec1 & !sel0 & !sel1 & !sel2);
_X017 = EXP( hour1 & !sel0 & !sel1 & sel2);
_EQ024 = _X016 & _X017;
_X016 = EXP( sec1 & !sel0 & !sel1 & !sel2);
_X017 = EXP( hour1 & !sel0 & !sel1 & sel2);
-- Node name is '~796~1'
-- Equation name is '~796~1', location is LC019, type is buried.
-- synthesized logic cell
_LC019 = LCELL( _EQ025 $ _EQ026);
_EQ025 = _LC012 & _LC053 & _LC054 & min4 & sel0 & sel1 & !sel2 &
_X018 & _X019
# hour4 & _LC012 & _LC053 & _LC054 & sel0 & !sel1 & sel2 &
_X018 & _X019
# _LC012 & _LC053 & _LC054 & sec4 & sel0 & !sel1 & !sel2 &
_X018 & _X019
# _LC012 & _LC053 & _LC054 & min0 & !sel0 & sel1 & !sel2 &
_X018 & _X019;
_X018 = EXP( sec0 & !sel0 & !sel1 & !sel2);
_X019 = EXP( hour0 & !sel0 & !sel1 & sel2);
_EQ026 = _LC012 & _LC053 & _LC054 & _X018 & _X019;
_X018 = EXP( sec0 & !sel0 & !sel1 & !sel2);
_X019 = EXP( hour0 & !sel0 & !sel1 & sel2);
-- Node name is '~797~1'
-- Equation name is '~797~1', location is LC027, type is buried.
-- synthesized logic cell
_LC027 = LCELL( _EQ027 $ _EQ028);
_EQ027 = min4 & sel0 & sel1 & !sel2 & _X018 & _X019
# hour4 & sel0 & !sel1 & sel2 & _X018 & _X019
# sec4 & sel0 & !sel1 & !sel2 & _X018 & _X019
# min0 & !sel0 & sel1 & !sel2 & _X018 & _X019;
_X018 = EXP( sec0 & !sel0 & !sel1 & !sel2);
_X019 = EXP( hour0 & !sel0 & !sel1 & sel2);
_EQ028 = _X018 & _X019;
_X018 = EXP( sec0 & !sel0 & !sel1 & !sel2);
_X019 = EXP( hour0 & !sel0 & !sel1 & sel2);
-- Node name is '~832~1'
-- Equation name is '~832~1', location is LC057, type is buried.
-- synthesized logic cell
_LC057 = LCELL( _EQ029 $ GND);
_EQ029 = !_LC038 & !min0 & !min1 & min2 & !min3 & !sel0 & sel1 & !sel2
# !hour0 & !hour1 & hour2 & !hour3 & !_LC038 & !sel0 & !sel1 &
sel2
# !_LC038 & !sec0 & !sec1 & sec2 & !sec3 & !sel0 & !sel1 & !sel2
# !_LC038 & !min4 & !min5 & min6 & sel0 & sel1 & !sel2
# !_LC038 & min0 & min1 & !min3 & !sel0 & sel1 & !sel2;
-- Node name is '~832~2'
-- Equation name is '~832~2', location is LC059, type is buried.
-- synthesized logic cell
_LC059 = LCELL( _EQ030 $ GND);
_EQ030 = hour0 & hour1 & !hour3 & !_LC038 & !sel0 & !sel1 & sel2
# !_LC038 & !sec4 & !sec5 & sec6 & sel0 & !sel1 & !sel2
# !_LC038 & sec0 & sec1 & !sec3 & !sel0 & !sel1 & !sel2
# !_LC038 & min4 & min5 & sel0 & sel1 & !sel2
# hour4 & hour5 & !_LC038 & sel0 & !sel1 & sel2;
-- Node name is '~865~1'
-- Equation name is '~865~1', location is LC055, type is buried.
-- synthesized logic cell
_LC055 = LCELL( _EQ031 $ GND);
_EQ031 = !hour1 & !hour2 & hour3 & !_LC038 & !_LC044 & !sel0 & !sel1 &
sel2
# !_LC038 & !_LC044 & !min1 & !min2 & min3 & !sel0 & sel1 & !sel2
# !_LC038 & !_LC044 & !sec1 & !sec2 & sec3 & !sel0 & !sel1 & !sel2
# hour2 & !hour3 & !_LC038 & !_LC044 & !sel0 & !sel1 & sel2
# !_LC038 & !_LC044 & min2 & !min3 & !sel0 & sel1 & !sel2;
-- Node name is '~865~2'
-- Equation name is '~865~2', location is LC041, type is buried.
-- synthesized logic cell
_LC041 = LCELL( _EQ032 $ GND);
_EQ032 = !_LC038 & !_LC044 & sec2 & !sec3 & !sel0 & !sel1 & !sel2
# !_LC038 & !_LC044 & min6 & sel0 & sel1 & !sel2
# !_LC038 & !_LC044 & sec6 & sel0 & !sel1 & !sel2
# !_LC038 & _LC039 & !_LC044;
-- Node name is '~898~1'
-- Equation name is '~898~1', location is LC058, type is buried.
-- synthesized logic cell
_LC058 = LCELL( _EQ033 $ GND);
_EQ033 = !hour0 & hour1 & hour2 & !hour3 & !_LC038 & !sel0 & !sel1 &
sel2
# !_LC038 & !min0 & min1 & min2 & !min3 & !sel0 & sel1 & !sel2
# hour0 & !hour1 & hour2 & !hour3 & !_LC038 & !sel0 & !sel1 &
sel2
# !_LC038 & min0 & !min1 & min2 & !min3 & !sel0 & sel1 & !sel2
# !_LC038 & !sec0 & sec1 & sec2 & !sec3 & !sel0 & !sel1 & !sel2;
-- Node name is '~898~2'
-- Equation name is '~898~2', location is LC042, type is buried.
-- synthesized logic cell
_LC042 = LCELL( _EQ034 $ GND);
_EQ034 = !_LC038 & sec0 & !sec1 & sec2 & !sec3 & !sel0 & !sel1 & !sel2
# !_LC038 & !min4 & min5 & min6 & sel0 & sel1 & !sel2
# !_LC038 & min4 & !min5 & min6 & sel0 & sel1 & !sel2
# !_LC038 & !sec4 & sec5 & sec6 & sel0 & !sel1 & !sel2
# !_LC038 & sec4 & !sec5 & sec6 & sel0 & !sel1 & !sel2;
-- Node name is '~898~3'
-- Equation name is '~898~3', location is LC061, type is buried.
-- synthesized logic cell
_LC061 = LCELL( _EQ035 $ GND);
_EQ035 = !_LC038 & !min1 & !min2 & min3 & !sel0 & sel1 & !sel2
# !hour1 & !hour2 & hour3 & !_LC038 & !sel0 & !sel1 & sel2
# !_LC038 & !sec1 & !sec2 & sec3 & !sel0 & !sel1 & !sel2
# !_LC038 & _LC044;
-- Node name is '~931~1'
-- Equation name is '~931~1', location is LC062, type is buried.
-- synthesized logic cell
_LC062 = LCELL( _EQ036 $ GND);
_EQ036 = !hour0 & hour1 & hour2 & !hour3 & !_LC039 & !sel0 & !sel1 &
sel2
# !_LC039 & !min0 & min1 & min2 & !min3 & !sel0 & sel1 & !sel2
# !_LC039 & !sec0 & sec1 & sec2 & !sec3 & !sel0 & !sel1 & !sel2
# !hour0 & !hour1 & !hour2 & hour3 & !_LC039 & !sel0 & !sel1 &
sel2
# !_LC039 & !min0 & !min1 & !min2 & min3 & !sel0 & sel1 & !sel2;
-- Node name is '~964~1'
-- Equation name is '~964~1', location is LC063, type is buried.
-- synthesized logic cell
_LC063 = LCELL( _EQ037 $ GND);
_EQ037 = !_LC039 & !_LC044 & !min0 & min2 & !min3 & !sel0 & sel1 & !sel2
# !hour0 & hour2 & !hour3 & !_LC039 & !_LC044 & !sel0 & !sel1 &
sel2
# !_LC039 & !_LC044 & !min1 & !min2 & min3 & !sel0 & sel1 & !sel2
# !hour1 & !hour2 & hour3 & !_LC039 & !_LC044 & !sel0 & !sel1 &
sel2
# !_LC039 & !_LC044 & !min1 & min2 & !min3 & !sel0 & sel1 & !sel2;
-- Node name is '~964~2'
-- Equation name is '~964~2', location is LC064, type is buried.
-- synthesized logic cell
_LC064 = LCELL( _EQ038 $ GND);
_EQ038 = !hour1 & hour2 & !hour3 & !_LC039 & !_LC044 & !sel0 & !sel1 &
sel2
# !_LC039 & !_LC044 & !sec0 & sec2 & !sec3 & !sel0 & !sel1 & !sel2
# !_LC039 & !_LC044 & !sec1 & !sec2 & sec3 & !sel0 & !sel1 & !sel2
# !_LC039 & !_LC044 & !sec1 & sec2 & !sec3 & !sel0 & !sel1 & !sel2
# !_LC039 & !_LC044 & !min4 & min6 & sel0 & sel1 & !sel2;
-- Node name is '~997~1'
-- Equation name is '~997~1', location is LC052, type is buried.
-- synthesized logic cell
_LC052 = LCELL( _EQ039 $ GND);
_EQ039 = !_LC019 & !_LC038 & !min0 & min2 & !min3 & !sel0 & sel1 & !sel2
# !hour0 & hour2 & !hour3 & !_LC019 & !_LC038 & !sel0 & !sel1 &
sel2
# !_LC019 & !_LC038 & !min1 & !min2 & min3 & !sel0 & sel1 & !sel2
# !hour1 & !hour2 & hour3 & !_LC019 & !_LC038 & !sel0 & !sel1 &
sel2
# !_LC019 & !_LC038 & !min1 & min2 & !min3 & !sel0 & sel1 & !sel2;
-- Node name is '~997~2'
-- Equation name is '~997~2', location is LC046, type is buried.
-- synthesized logic cell
_LC046 = LCELL( _EQ040 $ GND);
_EQ040 = !hour1 & hour2 & !hour3 & !_LC019 & !_LC038 & !sel0 & !sel1 &
sel2
# !_LC019 & !_LC038 & !sec0 & sec2 & !sec3 & !sel0 & !sel1 & !sel2
# !_LC019 & !_LC038 & !sec1 & !sec2 & sec3 & !sel0 & !sel1 & !sel2
# !_LC019 & !_LC038 & !sec1 & sec2 & !sec3 & !sel0 & !sel1 & !sel2
# !_LC019 & !_LC038 & !min4 & min6 & sel0 & sel1 & !sel2;
-- Node name is '~997~3'
-- Equation name is '~997~3', location is LC047, type is buried.
-- synthesized logic cell
_LC047 = LCELL( _EQ041 $ GND);
_EQ041 = !_LC019 & !_LC038 & !min5 & min6 & sel0 & sel1 & !sel2
# !_LC019 & !_LC038 & !sec4 & sec6 & sel0 & !sel1 & !sel2
# !_LC019 & !_LC038 & !sec5 & sec6 & sel0 & !sel1 & !sel2
# !_LC019 & !_LC038 & _LC039
# !_LC019 & !_LC038 & _LC044;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X009 occurs in LABs A, C
Project Information k:\timevhd\seltime_dc.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:11
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:05
-------------------------- --------
Total Time 00:00:19
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,743K
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