📄 seltime_dc.rpt
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** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------- LC24 s0
| +----------- LC25 s3
| | +--------- LC21 s4
| | | +------- LC20 s5
| | | | +----- LC17 s6
| | | | | +--- LC19 ~796~1
| | | | | | +- LC27 ~797~1
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'B'
LC | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC19 -> - * * * * - - | - * * * | <-- ~796~1
LC27 -> - - - - * - - | - * - - | <-- ~797~1
Pin
43 -> - - - - - - - | - - - - | <-- clk
31 -> - - - - - * * | - * - * | <-- hour0
12 -> - - - - - * * | * * * * | <-- hour4
2 -> - - - - - * * | - * - * | <-- min0
8 -> - - - - - * * | - * * * | <-- min4
44 -> - - - - - - - | - - * * | <-- min5
1 -> - - - - - - - | - - - - | <-- reset
20 -> - - - - - * * | - * * * | <-- sec0
6 -> - - - * - * * | - * * * | <-- sec4
5 -> - - - * - - - | - * * * | <-- sec5
LC36 -> - - - * - * * | * * * * | <-- sel0
LC40 -> - - - * - * * | * * * * | <-- sel1
LC37 -> - - - * - * * | * * * * | <-- sel2
LC39 -> - * - - - - - | - * * * | <-- ~760~1
LC14 -> - - - - * - - | - * - - | <-- ~775~1
LC38 -> - * - * * - - | - * * * | <-- ~784~1
LC54 -> - - - - * * - | - * - - | <-- ~791~1
LC12 -> - - - - * * - | - * - - | <-- ~793~1
LC53 -> - - - - * * - | - * - - | <-- ~795~1
LC57 -> - - - * - - - | - * - - | <-- ~832~1
LC59 -> - - - * - - - | - * - - | <-- ~832~2
LC55 -> - - * - - - - | - * - - | <-- ~865~1
LC41 -> - - * - - - - | - * - - | <-- ~865~2
LC58 -> - * - - - - - | - * - - | <-- ~898~1
LC42 -> - * - - - - - | - * - - | <-- ~898~2
LC61 -> - * - * - - - | - * - - | <-- ~898~3
LC52 -> * - - - - - - | - * - - | <-- ~997~1
LC46 -> * - - - - - - | - * - - | <-- ~997~2
LC47 -> * - - - - - - | - * - - | <-- ~997~3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: k:\timevhd\seltime_dc.rpt
seltime_dc
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------------- LC36 sel0
| +--------------------------- LC40 sel1
| | +------------------------- LC37 sel2
| | | +----------------------- LC33 s1
| | | | +--------------------- LC35 s2
| | | | | +------------------- LC39 ~760~1
| | | | | | +----------------- LC44 ~772~1
| | | | | | | +--------------- LC34 ~772~3
| | | | | | | | +------------- LC43 ~775~4
| | | | | | | | | +----------- LC48 ~775~5
| | | | | | | | | | +--------- LC38 ~784~1
| | | | | | | | | | | +------- LC41 ~865~2
| | | | | | | | | | | | +----- LC42 ~898~2
| | | | | | | | | | | | | +--- LC46 ~997~2
| | | | | | | | | | | | | | +- LC47 ~997~3
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC36 -> * * * * * * - * * * * * * * * | * * * * | <-- sel0
LC40 -> - * * * * * - * * * * * * * * | * * * * | <-- sel1
LC37 -> - - * * * * - * * * * * * * * | * * * * | <-- sel2
LC39 -> - - - * * - - - - - - * - - * | - * * * | <-- ~760~1
LC44 -> - - - * * - - - - - - * - - * | - - * * | <-- ~772~1
LC34 -> - - - - - - * - - - - - - - - | * - * - | <-- ~772~3
LC38 -> - - - * * - - - - - - * * * * | - * * * | <-- ~784~1
Pin
43 -> - - - - - - - - - - - - - - - | - - - - | <-- clk
37 -> - - - - - - - - - - - - - * - | - - * * | <-- hour1
33 -> - - - - - - - - - - - - - * - | * - * * | <-- hour2
39 -> - - - - - - - - - - - - - * - | - - * * | <-- hour3
12 -> - - - - - * - * - - * - - - - | * * * * | <-- hour4
29 -> - - - - - * - * - - * - - - - | * - * * | <-- hour5
2 -> - - - - - - - - - - - - - - - | - * - * | <-- min0
8 -> - - - - * * - * * - * - * * - | - * * * | <-- min4
44 -> - - - * * * - * * - * - * - * | - - * * | <-- min5
11 -> - - - * * * - * * - * * * * * | * - * * | <-- min6
1 -> - - - - - - - - - - - - - - - | - - - - | <-- reset
20 -> - - - - * - - - * - - - * * - | - * * * | <-- sec0
36 -> - - - - * - - - * - - - * * - | - - * * | <-- sec1
9 -> - - - - * - - - * - - * * * - | * - * * | <-- sec2
34 -> - - - - * - - - * - - * * * - | - - * * | <-- sec3
6 -> - - - * * * - * - * * - * - * | - * * * | <-- sec4
5 -> - - - * * * - * - * * - * - * | - * * * | <-- sec5
4 -> - - - * * * - * - * * * * - * | * - * * | <-- sec6
LC50 -> - - - - - * - - - - - - - - - | - - * - | <-- ~760~2
LC49 -> - - - - - - * - - - - - - - - | * - * - | <-- ~772~2
LC51 -> - - - - - - - - - - * - - - - | - - * - | <-- ~784~2
LC19 -> - - - * * - - - - - - - - * * | - * * * | <-- ~796~1
LC62 -> - - - - * - - - - - - - - - - | - - * - | <-- ~931~1
LC63 -> - - - * - - - - - - - - - - - | - - * - | <-- ~964~1
LC64 -> - - - * - - - - - - - - - - - | - - * - | <-- ~964~2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: k:\timevhd\seltime_dc.rpt
seltime_dc
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC50 ~760~2
| +----------------------------- LC49 ~772~2
| | +--------------------------- LC56 ~775~2
| | | +------------------------- LC60 ~775~3
| | | | +----------------------- LC51 ~784~2
| | | | | +--------------------- LC54 ~791~1
| | | | | | +------------------- LC53 ~795~1
| | | | | | | +----------------- LC57 ~832~1
| | | | | | | | +--------------- LC59 ~832~2
| | | | | | | | | +------------- LC55 ~865~1
| | | | | | | | | | +----------- LC58 ~898~1
| | | | | | | | | | | +--------- LC61 ~898~3
| | | | | | | | | | | | +------- LC62 ~931~1
| | | | | | | | | | | | | +----- LC63 ~964~1
| | | | | | | | | | | | | | +--- LC64 ~964~2
| | | | | | | | | | | | | | | +- LC52 ~997~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
31 -> * * * * * - - * * - * - * * - * | - * - * | <-- hour0
37 -> * * * * * - * * * * * * * * * * | - - * * | <-- hour1
33 -> * * * * * - - * - * * * * * * * | * - * * | <-- hour2
39 -> * * * * * * - * * * * * * * * * | - - * * | <-- hour3
12 -> * * - - * - - - * - - - - - - - | * * * * | <-- hour4
29 -> * * - - * - * - * - - - - - - - | * - * * | <-- hour5
2 -> * * * - * - - * - - * - * * - * | - * - * | <-- min0
40 -> * * * * * - * * - * * * * * - * | - - - * | <-- min1
14 -> * * * * * - - * - * * * * * - * | * - - * | <-- min2
41 -> * * * * * * - * - * * * * * - * | - - - * | <-- min3
8 -> * * - - * - - * * - - - - - * - | - * * * | <-- min4
44 -> * * - - * - * * * - - - - - - - | - - * * | <-- min5
11 -> * * - - * - - * - - - - - - * - | * - * * | <-- min6
1 -> - - - - - - - - - - - - - - - - | - - - - | <-- reset
20 -> * * - * * - - * * - * - * - * - | - * * * | <-- sec0
36 -> * * - * * - * * * * * * * - * - | - - * * | <-- sec1
9 -> * * - * * - - * - * * * * - * - | * - * * | <-- sec2
34 -> * * - * * * - * * * * * * - * - | - - * * | <-- sec3
6 -> * * - - * - - - * - - - - - - - | - * * * | <-- sec4
5 -> * * - - * - * - * - - - - - - - | - * * * | <-- sec5
4 -> * * - - * - - - * - - - - - - - | * - * * | <-- sec6
LC36 -> * * * * * * * * * * * * * * * * | * * * * | <-- sel0
LC40 -> * * * * * * * * * * * * * * * * | * * * * | <-- sel1
LC37 -> * * * * * * * * * * * * * * * * | * * * * | <-- sel2
LC39 -> - - - - - - - - - - - - * * * - | - * * * | <-- ~760~1
LC44 -> - - - - - - - - - * - * - * * - | - - * * | <-- ~772~1
LC38 -> - - - - - - - * * * * * - - - * | - * * * | <-- ~784~1
LC19 -> - - - - - - - - - - - - - - - * | - * * * | <-- ~796~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: k:\timevhd\seltime_dc.rpt
seltime_dc
** EQUATIONS **
clk : INPUT;
hour0 : INPUT;
hour1 : INPUT;
hour2 : INPUT;
hour3 : INPUT;
hour4 : INPUT;
hour5 : INPUT;
min0 : INPUT;
min1 : INPUT;
min2 : INPUT;
min3 : INPUT;
min4 : INPUT;
min5 : INPUT;
min6 : INPUT;
reset : INPUT;
sec0 : INPUT;
sec1 : INPUT;
sec2 : INPUT;
sec3 : INPUT;
sec4 : INPUT;
sec5 : INPUT;
sec6 : INPUT;
-- Node name is 'sel0' = 'tmpa0~162'
-- Equation name is 'sel0', location is LC036, type is output.
sel0 = TFFE( VCC, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
-- Node name is 'sel1' = 'tmpa1~162'
-- Equation name is 'sel1', location is LC040, type is output.
sel1 = TFFE( sel0, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
-- Node name is 'sel2' = 'tmpa2~162'
-- Equation name is 'sel2', location is LC037, type is output.
sel2 = TFFE( _EQ001, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ001 = sel0 & sel1;
-- Node name is 's0'
-- Equation name is 's0', location is LC024, type is output.
s0 = LCELL( _EQ002 $ VCC);
_EQ002 = !_LC046 & !_LC047 & !_LC052;
-- Node name is 's1'
-- Equation name is 's1', location is LC033, type is output.
s1 = LCELL( _EQ003 $ VCC);
_EQ003 = !_LC019 & !_LC038 & !_LC063 & !_LC064 & _X001 & _X002 & _X003;
_X001 = EXP(!_LC039 & !_LC044 & !min5 & min6 & sel0 & sel1 & !sel2);
_X002 = EXP(!_LC039 & !_LC044 & !sec4 & sec6 & sel0 & !sel1 & !sel2);
_X003 = EXP(!_LC039 & !_LC044 & !sec5 & sec6 & sel0 & !sel1 & !sel2);
-- Node name is 's2'
-- Equation name is 's2', location is LC035, type is output.
s2 = LCELL( _EQ004 $ VCC);
_EQ004 = !_LC019 & !_LC038 & !_LC044 & !_LC062 & _X004 & _X005 & _X006;
_X004 = EXP(!_LC039 & !sec0 & !sec1 & !sec2 & sec3 & !sel0 & !sel1 & !sel2);
_X005 = EXP(!_LC039 & !min4 & min5 & min6 & sel0 & sel1 & !sel2);
_X006 = EXP(!_LC039 & !sec4 & sec5 & sec6 & sel0 & !sel1 & !sel2);
-- Node name is 's3'
-- Equation name is 's3', location is LC025, type is output.
s3 = LCELL( _EQ005 $ VCC);
_EQ005 = !_LC019 & !_LC042 & !_LC058 & !_LC061 & _X007;
_X007 = EXP(!_LC038 & _LC039);
-- Node name is 's4'
-- Equation name is 's4', location is LC021, type is output.
s4 = LCELL( _EQ006 $ VCC);
_EQ006 = !_LC019 & !_LC041 & !_LC055;
-- Node name is 's5'
-- Equation name is 's5', location is LC020, type is output.
s5 = LCELL( _EQ007 $ VCC);
_EQ007 = !_LC019 & !_LC057 & !_LC059 & !_LC061 & _X008;
_X008 = EXP(!_LC038 & sec4 & sec5 & sel0 & !sel1 & !sel2);
-- Node name is 's6'
-- Equation name is 's6', location is LC017, type is output.
s6 = LCELL( _EQ008 $ GND);
_EQ008 = _LC012 & _LC027 & _LC053 & _LC054
# _LC014 & !_LC019 & !_LC038;
-- Node name is '~760~1'
-- Equation name is '~760~1', location is LC039, type is buried.
-- synthesized logic cell
_LC039 = LCELL( _EQ009 $ VCC);
_EQ009 = !_LC050 & _X009 & _X010 & _X011;
_X009 = EXP( hour4 & hour5 & sel0 & !sel1 & sel2);
_X010 = EXP( min4 & min5 & !min6 & sel0 & sel1 & !sel2);
_X011 = EXP( sec4 & sec5 & !sec6 & sel0 & !sel1 & !sel2);
-- Node name is '~760~2'
-- Equation name is '~760~2', location is LC050, type is buried.
-- synthesized logic cell
_LC050 = LCELL( _EQ010 $ GND);
_EQ010 = min0 & min1 & !min2 & !min3 & min4 & min5 & !min6 & sec0 &
sec1 & !sec2 & !sec3 & sec4 & sec5 & !sec6 & !sel2
# hour0 & hour1 & !hour2 & !hour3 & hour4 & hour5 & sec0 &
sec1 & !sec2 & !sec3 & sec4 & sec5 & !sec6 & !sel1
# min0 & min1 & !min2 & !min3 & !sel0 & sel1 & !sel2
# hour0 & hour1 & !hour2 & !hour3 & !sel0 & !sel1 & sel2
# sec0 & sec1 & !sec2 & !sec3 & !sel0 & !sel1 & !sel2;
-- Node name is '~772~1'
-- Equation name is '~772~1', location is LC044, type is buried.
-- synthesized logic cell
_LC044 = LCELL( _EQ011 $ VCC);
_EQ011 = !_LC034 & !_LC049;
-- Node name is '~772~2'
-- Equation name is '~772~2', location is LC049, type is buried.
-- synthesized logic cell
_LC049 = LCELL( _EQ012 $ GND);
_EQ012 = !min0 & min1 & !min2 & !min3 & !min4 & min5 & !min6 & !sec0 &
sec1 & !sec2 & !sec3 & !sec4 & sec5 & !sec6 & !sel2
# !hour0 & hour1 & !hour2 & !hour3 & !hour4 & hour5 & !sec0 &
sec1 & !sec2 & !sec3 & !sec4 & sec5 & !sec6 & !sel1
# !min0 & min1 & !min2 & !min3 & !sel0 & sel1 & !sel2
# !hour0 & hour1 & !hour2 & !hour3 & !sel0 & !sel1 & sel2
# !sec0 & sec1 & !sec2 & !sec3 & !sel0 & !sel1 & !sel2;
-- Node name is '~772~3'
-- Equation name is '~772~3', location is LC034, type is buried.
-- synthesized logic cell
_LC034 = LCELL( _EQ013 $ GND);
_EQ013 = !min4 & min5 & !min6 & sel0 & sel1 & !sel2
# !sec4 & sec5 & !sec6 & sel0 & !sel1 & !sel2
# !hour4 & hour5 & sel0 & !sel1 & sel2;
-- Node name is '~775~1'
-- Equation name is '~775~1', location is LC014, type is buried.
-- synthesized logic cell
_LC014 = LCELL( _EQ014 $ VCC);
_EQ014 = !_LC034 & !_LC043 & !_LC048 & !_LC049 & !_LC056 & !_LC060 & _X009;
_X009 = EXP( hour4 & hour5 & sel0 & !sel1 & sel2);
-- Node name is '~775~2'
-- Equation name is '~775~2', location is LC056, type is buried.
-- synthesized logic cell
_LC056 = LCELL( _EQ015 $ GND);
_EQ015 = hour1 & hour2 & !hour3 & !sel0 & !sel1 & sel2
# min1 & min2 & !min3 & !sel0 & sel1 & !sel2
# min0 & min1 & !min3 & !sel0 & sel1 & !sel2
# hour0 & hour1 & !hour3 & !sel0 & !sel1 & sel2
# min0 & min2 & !min3 & !sel0 & sel1 & !sel2;
-- Node name is '~775~3'
-- Equation name is '~775~3', location is LC060, type is buried.
-- synthesized logic cell
_LC060 = LCELL( _EQ016 $ GND);
_EQ016 = hour0 & hour2 & !hour3 & !sel0 & !sel1 & sel2
# sec1 & sec2 & !sec3 & !sel0 & !sel1 & !sel2
# !hour1 & !hour2 & hour3 & !sel0 & !sel1 & sel2
# !min1 & !min2 & min3 & !sel0 & sel1 & !sel2
# sec0 & sec1 & !sec3 & !sel0 & !sel1 & !sel2;
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