second.vhd

个人设计的基于VHDL的数字电子日历 在MAX+PLUSH软件平台上编译、仿真

LIBRARY ieee; 
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY second IS
	PORT(
         CLk,reset,setmin : IN  STD_LOGIC;
		 daout      : OUT STD_LOGIC_VECTOR(6 downto 0);
		 enmin      : OUT STD_LOGIC                   
        );
END second;

ARCHITECTURE a OF second IS
 BEGIN
  PROCESS (Clk)
     VARIABLE tmpa :STD_LOGIC_VECTOR(3 downto 0);
     VARIABLE tmpb :STD_LOGIC_VECTOR(2 downto 0);
  BEGIN
	IF reset='0' THEN  tmpb := "000"; tmpa := "0000";
    ELSE    IF (Clk'event AND Clk='1') THEN
               IF tmpa="1001" THEN 
                   tmpa:="0000";
                   IF tmpb="101" THEN tmpb:="000";
                   ELSE  tmpb:= tmpb+1; 
                   END IF;
                ELSE  tmpa := tmpa+1;
                END IF; 
             END IF;
   END IF;
	 daout(3 downto 0) <= tmpa; daout(6 downto 4)<= tmpb;   
     enmin<= ((not tmpb(0)) AND  (not tmpb(1))AND (not tmpb(2)) AND (not tmpa(0))  AND (not tmpa(1)) AND (not tmpa(2)) AND (not tmpa(3)))or (not setmin) ;
   END PROCESS ;
END a;