📄 clock_top.rpt
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Device-Specific Information: f:\ted\051226edaex\timevhd\clock_top.rpt
clock_top
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
65 - - B -- OUTPUT 0 1 0 0 daout0
66 - - B -- OUTPUT 0 1 0 0 daout1
67 - - B -- OUTPUT 0 1 0 0 daout2
69 - - A -- OUTPUT 0 1 0 0 daout3
70 - - A -- OUTPUT 0 1 0 0 daout4
71 - - A -- OUTPUT 0 1 0 0 daout5
72 - - A -- OUTPUT 0 1 0 0 daout6
16 - - A -- OUTPUT 0 1 0 0 enhour
78 - - - 24 OUTPUT 0 1 0 0 lamp0
79 - - - 24 OUTPUT 0 1 0 0 lamp1
80 - - - 23 OUTPUT 0 1 0 0 lamp2
53 - - - 20 OUTPUT 0 1 0 0 sel0
52 - - - 19 OUTPUT 0 1 0 0 sel1
51 - - - 18 OUTPUT 0 1 0 0 sel2
10 - - - 01 OUTPUT 0 1 0 0 setlp1
11 - - - 01 OUTPUT 0 1 0 0 setlp2
73 - - A -- OUTPUT 0 1 0 0 speak
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\ted\051226edaex\timevhd\clock_top.rpt
clock_top
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 24 DFFE 1 2 1 0 |alert:ic5|speak_b (|alert:ic5|:15)
- 8 - B 24 DFFE 1 3 0 3 |alert:ic5|lamp_b1 (|alert:ic5|:16)
- 5 - B 24 DFFE 1 2 0 4 |alert:ic5|lamp_b0 (|alert:ic5|:17)
- 2 - B 19 AND2 s 0 3 0 1 |alert:ic5|~60~1
- 3 - B 24 AND2 s ! 0 4 0 4 |alert:ic5|~60~2
- 7 - B 24 OR2 ! 0 2 1 0 |alert:ic5|:173
- 4 - B 24 OR2 ! 0 2 1 0 |alert:ic5|:181
- 6 - B 24 AND2 0 2 1 0 |alert:ic5|:194
- 5 - B 02 DFFE 2 1 0 3 |clock_con:ic0|temp1 (|clock_con:ic0|:6)
- 8 - B 02 DFFE 2 1 0 2 |clock_con:ic0|temp0 (|clock_con:ic0|:7)
- 4 - B 02 AND2 ! 1 2 1 1 |clock_con:ic0|:244
- 3 - B 02 AND2 ! 1 1 1 1 |clock_con:ic0|:261
- 7 - B 17 OR2 ! 0 2 0 3 |hour:ic3|LPM_ADD_SUB:92|addcore:adder|:55
- 5 - B 17 DFFE 1 4 0 3 |hour:ic3|tmpa3~123 (|hour:ic3|:55)
- 8 - B 17 DFFE 1 3 0 4 |hour:ic3|tmpa2~123 (|hour:ic3|:56)
- 2 - B 17 DFFE 1 3 0 3 |hour:ic3|tmpa1~123 (|hour:ic3|:57)
- 1 - B 17 DFFE 1 1 0 4 |hour:ic3|tmpa0~123 (|hour:ic3|:58)
- 7 - B 02 DFFE 1 4 0 2 |hour:ic3|tmpb1~121 (|hour:ic3|:59)
- 2 - B 02 DFFE 1 2 0 3 |hour:ic3|tmpb0~121 (|hour:ic3|:60)
- 3 - B 17 AND2 0 4 0 3 |hour:ic3|:71
- 6 - B 02 OR2 s 0 3 0 1 |hour:ic3|~84~1
- 4 - B 17 OR2 s 0 4 0 4 |hour:ic3|~110~1
- 3 - B 19 DFFE 1 4 0 3 |minute:ic2|tmpa3~243 (|minute:ic2|:88)
- 4 - B 19 DFFE 1 4 0 4 |minute:ic2|tmpa2~243 (|minute:ic2|:89)
- 1 - B 19 DFFE 1 3 0 5 |minute:ic2|tmpa1~243 (|minute:ic2|:90)
- 2 - B 24 DFFE 1 1 0 9 |minute:ic2|tmpa0~243 (|minute:ic2|:91)
- 8 - B 19 DFFE 1 4 0 3 |minute:ic2|tmpb2~241 (|minute:ic2|:92)
- 6 - B 19 DFFE 1 4 0 3 |minute:ic2|tmpb1~241 (|minute:ic2|:93)
- 5 - B 19 DFFE 1 2 0 4 |minute:ic2|tmpb0~241 (|minute:ic2|:94)
- 7 - B 19 OR2 ! 0 4 0 5 |minute:ic2|:103
- 1 - B 02 OR2 0 3 1 6 |minute:ic2|:275
- 4 - B 22 DFFE 2 3 0 4 |second:ic1|tmpa3~243 (|second:ic1|:88)
- 3 - B 22 DFFE 2 2 0 5 |second:ic1|tmpa2~243 (|second:ic1|:89)
- 2 - B 22 DFFE 2 3 0 5 |second:ic1|tmpa1~243 (|second:ic1|:90)
- 1 - B 16 DFFE 2 0 0 6 |second:ic1|tmpa0~243 (|second:ic1|:91)
- 2 - B 16 DFFE 2 3 0 3 |second:ic1|tmpb2~241 (|second:ic1|:92)
- 4 - B 16 DFFE 2 3 0 3 |second:ic1|tmpb1~241 (|second:ic1|:93)
- 3 - B 16 DFFE 2 1 0 4 |second:ic1|tmpb0~241 (|second:ic1|:94)
- 6 - B 16 OR2 ! 0 4 0 3 |second:ic1|:103
- 7 - B 16 AND2 s 0 3 0 1 |second:ic1|~272~1
- 8 - B 16 AND2 s 0 3 0 1 |second:ic1|~272~2
- 5 - B 16 OR2 0 4 0 7 |second:ic1|:275
- 4 - B 18 DFFE 2 2 1 6 |seltime_dc:ic4|tmpa2~162 (|seltime_dc:ic4|:47)
- 1 - B 20 DFFE 2 1 1 7 |seltime_dc:ic4|tmpa1~162 (|seltime_dc:ic4|:48)
- 3 - B 20 DFFE 2 0 1 8 |seltime_dc:ic4|tmpa0~162 (|seltime_dc:ic4|:49)
- 6 - B 18 OR2 ! 0 3 0 2 |seltime_dc:ic4|:313
- 8 - B 18 OR2 ! 0 3 0 4 |seltime_dc:ic4|:323
- 5 - B 18 OR2 ! 0 3 0 3 |seltime_dc:ic4|:333
- 7 - B 18 OR2 ! 0 3 0 4 |seltime_dc:ic4|:343
- 2 - B 20 OR2 0 4 0 1 |seltime_dc:ic4|:346
- 3 - B 18 OR2 ! 0 3 0 5 |seltime_dc:ic4|:353
- 2 - B 18 OR2 ! 0 3 0 4 |seltime_dc:ic4|:363
- 5 - B 20 OR2 0 4 0 8 |seltime_dc:ic4|:366
- 6 - B 17 OR2 ! 0 4 0 1 |seltime_dc:ic4|:378
- 1 - B 23 OR2 ! 0 2 0 1 |seltime_dc:ic4|:385
- 2 - B 23 OR2 ! 0 4 0 1 |seltime_dc:ic4|:386
- 8 - B 23 OR2 ! 0 4 0 8 |seltime_dc:ic4|:387
- 5 - B 22 OR2 ! 0 4 0 1 |seltime_dc:ic4|:396
- 6 - B 22 OR2 ! 0 3 0 1 |seltime_dc:ic4|:399
- 7 - B 22 OR2 ! 0 3 0 1 |seltime_dc:ic4|:402
- 8 - B 22 OR2 ! 0 3 0 1 |seltime_dc:ic4|:405
- 1 - B 22 OR2 ! 0 3 0 8 |seltime_dc:ic4|:408
- 1 - B 18 OR2 0 4 0 1 |seltime_dc:ic4|:417
- 6 - B 20 OR2 0 3 0 1 |seltime_dc:ic4|:420
- 7 - B 20 OR2 0 3 0 1 |seltime_dc:ic4|:423
- 8 - B 20 OR2 0 3 0 1 |seltime_dc:ic4|:426
- 4 - B 20 OR2 0 3 0 6 |seltime_dc:ic4|:429
- 3 - B 23 OR2 0 4 1 0 |seltime_dc:ic4|:799
- 4 - B 15 OR2 0 4 1 0 |seltime_dc:ic4|:832
- 5 - B 23 OR2 0 4 1 0 |seltime_dc:ic4|:865
- 8 - B 15 OR2 0 4 1 0 |seltime_dc:ic4|:898
- 1 - B 15 OR2 0 4 1 0 |seltime_dc:ic4|:931
- 7 - B 15 OR2 0 4 0 2 |seltime_dc:ic4|:952
- 3 - B 15 OR2 0 3 1 0 |seltime_dc:ic4|:964
- 2 - B 15 AND2 s 0 3 0 2 |seltime_dc:ic4|~991~1
- 6 - B 15 OR2 s 0 3 0 2 |seltime_dc:ic4|~999~1
- 5 - B 15 OR2 0 3 1 0 |seltime_dc:ic4|:999
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\ted\051226edaex\timevhd\clock_top.rpt
clock_top
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 1/ 48( 2%) 5/ 48( 10%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
B: 21/ 96( 21%) 2/ 48( 4%) 29/ 48( 60%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\ted\051226edaex\timevhd\clock_top.rpt
clock_top
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 12 clk
LCELL 7 |minute:ic2|:275
LCELL 7 |second:ic1|:275
INPUT 3 clkdsp
Device-Specific Information: f:\ted\051226edaex\timevhd\clock_top.rpt
clock_top
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 23 reset
Device-Specific Information: f:\ted\051226edaex\timevhd\clock_top.rpt
clock_top
** EQUATIONS **
clk : INPUT;
clkdsp : INPUT;
model : INPUT;
reset : INPUT;
set : INPUT;
-- Node name is 'daout0'
-- Equation name is 'daout0', type is output
daout0 = _LC5_B15;
-- Node name is 'daout1'
-- Equation name is 'daout1', type is output
daout1 = _LC3_B15;
-- Node name is 'daout2'
-- Equation name is 'daout2', type is output
daout2 = _LC1_B15;
-- Node name is 'daout3'
-- Equation name is 'daout3', type is output
daout3 = _LC8_B15;
-- Node name is 'daout4'
-- Equation name is 'daout4', type is output
daout4 = _LC5_B23;
-- Node name is 'daout5'
-- Equation name is 'daout5', type is output
daout5 = _LC4_B15;
-- Node name is 'daout6'
-- Equation name is 'daout6', type is output
daout6 = _LC3_B23;
-- Node name is 'enhour'
-- Equation name is 'enhour', type is output
enhour = _LC1_B2;
-- Node name is 'lamp0'
-- Equation name is 'lamp0', type is output
lamp0 = _LC4_B24;
-- Node name is 'lamp1'
-- Equation name is 'lamp1', type is output
lamp1 = _LC7_B24;
-- Node name is 'lamp2'
-- Equation name is 'lamp2', type is output
lamp2 = _LC6_B24;
-- Node name is 'sel0'
-- Equation name is 'sel0', type is output
sel0 = _LC3_B20;
-- Node name is 'sel1'
-- Equation name is 'sel1', type is output
sel1 = _LC1_B20;
-- Node name is 'sel2'
-- Equation name is 'sel2', type is output
sel2 = _LC4_B18;
-- Node name is 'setlp1'
-- Equation name is 'setlp1', type is output
setlp1 = _LC4_B2;
-- Node name is 'setlp2'
-- Equation name is 'setlp2', type is output
setlp2 = _LC3_B2;
-- Node name is 'speak'
-- Equation name is 'speak', type is output
speak = _LC1_B24;
-- Node name is '|alert:ic5|:17' = '|alert:ic5|lamp_b0'
-- Equation name is '_LC5_B24', type is buried
_LC5_B24 = DFFE( _EQ001, clk, VCC, VCC, VCC);
_EQ001 = _LC2_B24 & _LC5_B24
# _LC3_B24 & _LC5_B24
# !_LC2_B24 & !_LC3_B24 & !_LC5_B24;
-- Node name is '|alert:ic5|:16' = '|alert:ic5|lamp_b1'
-- Equation name is '_LC8_B24', type is buried
_LC8_B24 = DFFE( _EQ002, clk, VCC, VCC, VCC);
_EQ002 = !_LC5_B24 & _LC8_B24
# !_LC2_B24 & !_LC3_B24 & _LC5_B24 & !_LC8_B24
# _LC2_B24 & _LC8_B24
# _LC3_B24 & _LC8_B24;
-- Node name is '|alert:ic5|:15' = '|alert:ic5|speak_b'
-- Equation name is '_LC1_B24', type is buried
_LC1_B24 = DFFE( _EQ003, clk, VCC, VCC, VCC);
_EQ003 = !_LC1_B24 & !_LC2_B24 & !_LC3_B24
# _LC1_B24 & _LC3_B24;
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