pinlvji.vhd

利用VHDL语言写的0到100MHZ频率计

--**************四档频率计******************——

----------------------显示（数码管）元件1--------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;

entity xianshi is
  port(suocun: in  std_logic;
       datain: in  std_logic_vector(3 downto 0);
       dataout:out std_logic_vector(6 downto 0)
       );
 end xianshi;

architecture rtl of xianshi is
  begin
    process(suocun)
     begin
      if(suocun'event and suocun='0')then
         case datain is
           when "0000"=>dataout<="1000000";
           when "0001"=>dataout<="1111001";
           when "0010"=>dataout<="0100100";
           when "0011"=>dataout<="0110000";
           when "0100"=>dataout<="0011001";
           when "0101"=>dataout<="0010010";
           when "0110"=>dataout<="0000010";
           when "0111"=>dataout<="1111000";
           when "1000"=>dataout<="0000000";
           when "1001"=>dataout<="0010000";
           when others=>dataout<="0111111";
       end case;
      end if;
   end process;
end rtl ;

--------------------元件2：十进制计数器1---------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dcount is
  port(resetx:in std_logic;
       clkinx:in std_logic;
       signx: in std_logic;
       countx:buffer std_logic_vector(3 downto 0)
      );
end dcount;

architecture rtl of dcount is
  --signal countxsign:std_logic_vector(3 downto 0); --未用
  begin
    process(resetx,clkinx,signx)
       begin
         if (resetx='0' or clkinx='0') then
            countx<="0000";       --改为异步清零
           elsif(signx'event and signx='0')then
               if(countx="1001")then
                  countx<="0000";
                else countx<=countx+'1';
               end if;
          end if;    
    end process;
 end rtl;


--------------------元件3：十进制计数器1，最高位溢出（指示）用---------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dhcount is
  port(reseth:in std_logic;
       clkinh:in std_logic;
       signh: in std_logic;
       counth:buffer std_logic_vector(3 downto 0)
      );
end dhcount;

architecture rtl of dhcount is
  --signal countxsign:std_logic_vector(3 downto 0); --未用
  begin
    process(reseth,clkinh,signh)
       begin
         if (reseth='0' or clkinh='0') then
            counth<="0000";       --改为异步清零
           elsif(signh'event and signh='0')then
               if(counth="1010")then
                  counth<="1010";
                else counth<=counth+'1';
               end if;
          end if;    
    end process;
 end rtl;
            
------------------------------元件4：分频元件---------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fenpin is
   port(clk:    in std_logic;
        reset:  in std_logic;
        fpcount:buffer std_logic_vector(2 downto 0);
        clkout: buffer std_logic
        );
 end fenpin;

architecture rtl of fenpin is
begin
  process(reset,clk)
    begin
       if(reset='0')then
         fpcount<="000";
         clkout<='0';
        elsif(clk'event and clk='1')then
           if(fpcount="100")then
              fpcount<="000";
              clkout<= not clkout;
           else fpcount<=fpcount+'1'; 
           end if;
        end if;
  end process;
end rtl;
      
                

-------------------------------------------------主代码---------------------------------------------------
----------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
  --实体---
entity pinlvji is
  port(clk:  in std_logic;
       sign: in std_logic;
       reset:in std_logic;
       key:  in std_logic;
       led1: out std_logic_vector(6 downto 0);
       led2: out std_logic_vector(6 downto 0);
       led3: out std_logic_vector(6 downto 0);
       led4: out std_logic_vector(6 downto 0);
       led5: out std_logic_vector(6 downto 0);
       led6: out std_logic_vector(6 downto 0);
       --clkout:buffer std_logic;
       clkinall:buffer std_logic;
       --clkinall1:out std_logic         --fang zheng yong
       ceshi:buffer std_logic_vector(3 downto 0);    --------测试用引脚
       ceshi_1: buffer std_logic;
       ceshi_2:buffer std_logic_vector(3 downto 0)
      );
end pinlvji;
  
-------------------结构体----------------------------
architecture pinlvji of pinlvji is
             ----显示元件例化------
   component xianshi is
      port(suocun :in std_logic;
           datain :in std_logic_vector(3 downto 0);
           dataout:out std_logic_vector(6 downto 0)
          );
   end component;

   component dcount is
      port(resetx:in std_logic;
           clkinx:in std_logic;
           signx: in std_logic;
           countx:buffer std_logic_vector(3 downto 0)
          );
   end component;

  component dhcount is
    port(reseth:in std_logic;
         clkinh:in std_logic;
         signh:in std_logic;
         counth:buffer std_logic_vector(3 downto 0)
        );
  end component;

 component fenpin is
   port(clk:in std_logic;
        reset:in std_logic;
        fpcount:buffer std_logic_vector(2 downto 0);
        clkout:out std_logic
       );
  end component;
   

--------------------------信号定义----------------------------
   
    signal count4:    std_logic_vector(11 downto 0);     --第四档量程闸门时间计数器————
    signal count3:    std_logic_vector(2 downto 0);      --第三档量程闸门时间计数器
    signal count2:    std_logic_vector(2 downto 0);      --第二档量程闸门时间计数器
    signal count1:    std_logic_vector(2 downto 0);      --第一档量程闸门时间计数器
    signal clkin4,clkin3,clkin2,clkin1: std_logic;       --四档 闸门信号
    signal countout1:    std_logic_vector(3 downto 0);   --对外加信号计数的计数器
    signal countout2:    std_logic_vector(3 downto 0);   ----//
    signal countout3:    std_logic_vector(3 downto 0);   ----//
    signal countout4:    std_logic_vector(3 downto 0);   ----//
    signal countout5:    std_logic_vector(3 downto 0);   ----//
    signal xscount:      std_logic_vector(3 downto 0);   ----用来显示量程的计数器
    signal stcount:      std_logic_vector(1 downto 0);   ----状态计数器


begin 

------------------状态计数器------------------------
statecount:process(key,reset)
   begin
     if(reset='0')then
       stcount<="00";
      elsif(key'event and key='1')then
         stcount<=stcount+'1';
     end if;
  end process statecount;
---------------不同状态的参数设置----------------------     

  statex: process(stcount)
     begin
          case stcount is
             when "00"=>  clkinall<=clkin1;xscount<="0001"; 
             when "01"=>  clkinall<=clkin2;xscount<="0001"; 
             when "10"=>  clkinall<=clkin3;xscount<="0010"; 
             when "11"=>  clkinall<=clkin4;xscount<="0011"; 
             when others=>null;
          end case;
  end process statex;

  fenpin_4: process(clk,reset)
     begin
      --if(clk'event and clk='1')then
         if(reset='0')then
           count4<=(others=>'0');
          elsif(clk'event and clk='1')then
          if(count4="111110100000")then   
            --if(count4="000011111111")then  --为了仿真把时间改小
               count4<=(others=>'0');
               clkin4<=not clkin4;
              -- clkout<=clkin4;            --fangzheng yong
           else count4<=count4+'1';
          end if;
       end if;
    end process fenpin_4;

-----------------------------元件例化-------------------------


 fenpin_3: fenpin port map(clkin4,reset,count3,clkin3);             --第三档量程选择闸门信号
 fenpin_2: fenpin port map(clkin3,reset,count2,clkin2);             --第二档量程选择闸门信号
 fenpin_1: fenpin port map(clkin2,reset,count1,clkin1);             --第一档量程选择闸门信号

 dcount1:  dcount port map(reset,clkinall,sign        ,countout1);  --五个单独的十进制计数器
 dcount2:  dcount port map(reset,clkinall,countout1(3),countout2);
 dcount3:  dcount port map(reset,clkinall,countout2(3),countout3);
 dcount4:  dcount port map(reset,clkinall,countout3(3),countout4);
 dhcount5: dcount port map(reset,clkinall,countout4(3),countout5);


 xianshi1: xianshi port map(clkinall,xscount,  led1);               --六个数码管显示，静态显示
 xianshi2: xianshi port map(clkinall,countout1,led2);
 xianshi3: xianshi port map(clkinall,countout2,led3);
 xianshi4: xianshi port map(clkinall,countout3,led4);
 xianshi5: xianshi port map(clkinall,countout4,led5);
 xianshi6: xianshi port map(clkinall,countout5,led6);


----------------------仿真时用测试点----------------------------
 -- ceshi<="1000";
 --clkinall1<=clkin4;
 --clkout<=clkinall;
 ceshi<=countout2;
 ceshi_1<=countout1(3);
 ceshi_2<=countout1; 



 end pinlvji;                                                       --工程结束