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pWTCON EQU 0x01D30000pINTCON EQU 0x01E00000pINTMSK EQU 0x01E0000CpLOCKTIME EQU 0x01D8000CpPLLCON EQU 0x01D80000pCLKCON EQU 0x01D80004pBWSCON EQU 0x01C80000vINTCON EQU 0x01 ;vector irq_enable fiq_disablevPLLCON EQU 0x098022 ;160:4:2 crystal=4MHz MCK=40MhzvCLKCON EQU 0x5FF8vLOCKTIME EQU 800DW8 EQU (0x0) ;data width 8DW16 EQU (0x1) ;data width 16DW32 EQU (0x2) ;data width 32WAIT EQU (0x1<<2) ;enable waitUBLB EQU (0x1<<3) ;enable UB/LBB1_BWSCON EQU ((DW16)<<4)B2_BWSCON EQU ((DW16)<<8)B3_BWSCON EQU ((DW16)<<12)B4_BWSCON EQU ((DW16)<<16)B5_BWSCON EQU ((DW16)<<20)B6_BWSCON EQU ((DW16)<<24)B7_BWSCON EQU ((DW16)<<28)vBWSCON EQU (B1_BWSCON+B2_BWSCON+B3_BWSCON+B4_BWSCON+B5_BWSCON+B6_BWSCON+B7_BWSCON)B0_Tacs EQU (0x0<<13) ;0clk BANKCON0B0_Tcos EQU (0x0<<11) ;0clkB0_Tacc EQU (0x4<<8) ;6clkB0_Tcoh EQU (0x0<<6) ;0clkB0_Tah EQU (0x0<<4) ;0clkB0_Tacp EQU (0x0<<2) ;0clkB0_PMC EQU (0x0) ;normalB1_Tacs EQU (0x0<<13) ;0clk BANKCON1B1_Tcos EQU (0x0<<11) ;0clkB1_Tacc EQU (0x7<<8) ;14clkB1_Tcoh EQU (0x0<<6) ;0clkB1_Tah EQU (0x0<<4) ;0clkB1_Tacp EQU (0x0<<2) ;0clkB1_PMC EQU (0x0) ;normalB2_Tacs EQU (0x0<<13) ;0clk BANKCON2B2_Tcos EQU (0x1<<11) ;1clkB2_Tacc EQU (0x6<<8) ;8clkB2_Tcoh EQU (0x1<<6) ;1clkB2_Tah EQU (0x0<<4) ;0clkB2_Tacp EQU (0x0<<2) ;0clkB2_PMC EQU (0x0) ;normalB3_Tacs EQU (0x0<<13) ;0clk BANKCON3B3_Tcos EQU (0x0<<11) ;0clkB3_Tacc EQU (0x7<<8) ;14clkB3_Tcoh EQU (0x0<<6) ;0clkB3_Tah EQU (0x0<<4) ;0clkB3_Tacp EQU (0x0<<2) ;0clkB3_PMC EQU (0x0) ;normalB4_Tacs EQU (0x0<<13) ;0clk BANKCON4B4_Tcos EQU (0x0<<11) ;0clkB4_Tacc EQU (0x7<<8) ;14clkB4_Tcoh EQU (0x0<<6) ;0clkB4_Tah EQU (0x0<<4) ;0clkB4_Tacp EQU (0x0<<2) ;0clkB4_PMC EQU (0x0) ;normalB5_Tacs EQU (0x0<<13) ;0clk BANKCON5B5_Tcos EQU (0x0<<11) ;0clkB5_Tacc EQU (0x7<<8) ;14clkB5_Tcoh EQU (0x0<<6) ;0clkB5_Tah EQU (0x0<<4) ;0clkB5_Tacp EQU (0x0<<2) ;0clkB5_PMC EQU (0x0) ;normalB6_MT EQU (0x3<<15) ;SDRAM BANKCON6B6_Trcd EQU (0x0<<2) ;2clkB6_SCAN EQU (0x0) ;8bitB7_MT EQU (0x3<<15) ;SDRAM BANKCON7B7_Trcd EQU (0x0<<2) ;2clkB7_SCAN EQU (0x0) ;8bitvB0 EQU (B0_Tacs+B0_Tcos+B0_Tacc+B0_Tcoh+B0_Tah+B0_Tacp+B0_PMC)vB1 EQU (B1_Tacs+B1_Tcos+B1_Tacc+B1_Tcoh+B1_Tah+B1_Tacp+B1_PMC)vB2 EQU (B2_Tacs+B2_Tcos+B2_Tacc+B2_Tcoh+B2_Tah+B2_Tacp+B2_PMC)vB3 EQU (B3_Tacs+B3_Tcos+B3_Tacc+B3_Tcoh+B3_Tah+B3_Tacp+B3_PMC)vB4 EQU (B4_Tacs+B4_Tcos+B4_Tacc+B4_Tcoh+B4_Tah+B4_Tacp+B4_PMC)vB5 EQU (B5_Tacs+B5_Tcos+B5_Tacc+B5_Tcoh+B5_Tah+B5_Tacp+B5_PMC)vB6 EQU (B6_MT+B6_Trcd+B6_SCAN)vB7 EQU (B7_MT+B7_Trcd+B7_SCAN)REFEN EQU (0x1<<23) ;refresh enableTREFMD EQU (0x0<<22) ;CBR(CAS before RAS)/Auto refreshTrp EQU (0x0<<20) ;2clkTsrc EQU (0x0<<18) ;4clkREFCNT EQU (1425) ;period=15.6us, MCLK=40Mhz, (2048+1-15.6*40)vREFRESH EQU (REFEN+TREFMD+Trp+Tsrc+REFCNT)vBANKSIZE EQU 0x10vMRSRB6 EQU 0x20vMRSRB7 EQU 0x20USRMODE EQU 0x10FIQMODE EQU 0x11IRQMODE EQU 0x12SVCMODE EQU 0x13ABORTMODE EQU 0x17UNDEFMODE EQU 0x1bMODEMASK EQU 0x1fNOINT EQU 0xc0SC_SVCSTACK EQU 0x0C7A0000SC_IRQSTACK EQU 0x0C7C0000SC_FIQSTACK EQU 0x0C7E0000COPY_SIZE EQU 0x0003FFFFROM_START EQU 0x00000000RAM_START EQU 0x0C000000 IMPORT |Image$$RO$$Base| ;begin of ro IMPORT |Image$$RW$$Limit| ;end of rw IMPORT |Image$$ZI$$Base| ;begin of zi IMPORT |Image$$ZI$$Limit| ;enf of zi IMPORT main_start ;c code entry IMPORT isr_eint3 ;isr EXPORT _start AREA INIT,CODE,READONLY ENTRY_start B _reset ;0x00 reset B _reset ;0x04 undef B _reset ;0x08 swi B _reset ;0x0C pabort B _reset ;0x10 dabort B _reset ;0x14 unused B . ;0x18 irq B _reset ;0x1C fiq_vector B . ;0x20 eint0 B . ;0x24 eint1 B . ;0x28 eint2 LDR PC,=isr_eint3 ;0x3C eint3 B . ;0x30 eint4567 B . ;0x34 tick B . B . B . ;0x40 zdma0 B . ;0x44 zdma1 B . ;0x48 bdma0 B . ;0x4C bdma1 B . ;0x50 wdt B . ;0x54 uerr01 B . B . B . ;0x60 timer0 B . ;0x64 timer1 B . ;0x68 timer2 B . ;0x6C timer3 B . ;0x70 timer4 B . ;0x74 timer5 B . B . B . ;0x80 urxd0 B . ;0x84 urxd1 B . ;0x88 iic B . ;0x8C sio B . ;0x90 utxd0 B . ;0x94 utxd1 B . B . B . ;0xa0 rtc B . B . B . B . B . B . B . B . ;0xb0 adc B . B . B . B . B . B . B . B . ;0xc0 powerdown LTORG_mm_con_reg DCD vBWSCON DCD vB0 DCD vB1 DCD vB2 DCD vB3 DCD vB4 DCD vB5 DCD vB6 DCD vB7 DCD vREFRESH DCD vBANKSIZE DCD vMRSRB6 DCD vMRSRB7_reset LDR R0,=pWTCON ;watch dog disable LDR R1,=0x0 STR R1,[R0] LDR R0,=pINTMSK ;all interrupt disable LDR R1,=0x07FFFFFF STR R1,[R0] LDR R0,=pINTCON ;interrupt mode LDR R1,=vINTCON STR R1,[R0] LDR R0,=pLOCKTIME ;clock control registers LDR R1,=800 STR R1,[R0] LDR R0,=pPLLCON LDR R1,=vPLLCON STR R1,[R0] LDR R0,=pCLKCON LDR R1,=vCLKCON STR R1,[R0] ADR R0,_mm_con_reg ;memory control registers LDMIA R0,{R1-R13} LDR R0,=pBWSCON STMIA R0,{R1-R13}_relocate ADR R0,_start LDR R1,=|Image$$RO$$Base| LDR R2,=|Image$$RW$$Limit| SUB R2,R2,R1 ADD R2,R0,R2 LDR R1,=RAM_START_copy_loop LDMIA R0!,{R3-R10} STMIA R1!,{R3-R10} CMP R0,R2 BLT _copy_loop_init_zi LDR R0,=|Image$$ZI$$Base| LDR R2,=|Image$$ZI$$Limit| LDR R1,=0_zero_loop STMIA R0!,{R1} CMP R0,R2 BLT _zero_loop_init_stacks MRS R0,CPSR ;initializate stacks BIC R0,R0,#MODEMASK|NOINT ORR R1,R0,#IRQMODE MSR CPSR_cxsf,R1 LDR SP,=SC_IRQSTACK ORR R1,R0,#FIQMODE MSR CPSR_cxsf,R1 LDR SP,=SC_FIQSTACK ORR R1,R0,#SVCMODE MSR CPSR_cxsf,R1 LDR SP,=SC_SVCSTACK_goto_main LDR PC,_main_start_main_start DCD main_start LTORG END⌨️ 快捷键说明
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