📄 s3c44b0.h
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#ifndef __S3C44B0_H__#define __S3C44B0_H__#define REGBASE 0x01c00000#define REGL(addr) (*(volatile unsigned int *)(REGBASE+addr))#define REGW(addr) (*(volatile unsigned short *)(REGBASE+addr))#define REGB(addr) (*(volatile unsigned char *)(REGBASE+addr))/*****************************//* CPU Wrapper Registers *//*****************************/#define rSYSCFG REGL(0x000000)#define rNCACHBE0 REGL(0x000004)#define rNCACHBE1 REGL(0x000008)#define rSBUSCON REGL(0x040000)/************************************//* Memory Controller Registers *//************************************/#define rBWSCON REGL(0x080000)#define rBANKCON0 REGL(0x080004)#define rBANKCON1 REGL(0x080008)#define rBANKCON2 REGL(0x08000c)#define rBANKCON3 REGL(0x080010)#define rBANKCON4 REGL(0x080014)#define rBANKCON5 REGL(0x080018)#define rBANKCON6 REGL(0x08001c)#define rBANKCON7 REGL(0x080020)#define rREFRESH REGL(0x080024)#define rBANKSIZE REGL(0x080028)#define rMRSRB6 REGL(0x08002c)#define rMRSRB7 REGL(0x080030)/*********************//* UART Registers *//*********************/#define rULCON0 REGL(0x100000)#define rULCON1 REGL(0x104000)#define rUCON0 REGL(0x100004)#define rUCON1 REGL(0x104004)#define rUFCON0 REGL(0x100008)#define rUFCON1 REGL(0x104008)#define rUMCON0 REGL(0x10000c)#define rUMCON1 REGL(0x10400c)#define rUTRSTAT0 REGL(0x100010)#define rUTRSTAT1 REGL(0x104010)#define rUERSTAT0 REGL(0x100014)#define rUERSTAT1 REGL(0x104014)#define rUFSTAT0 REGL(0x100018)#define rUFSTAT1 REGL(0x104018)#define rUMSTAT0 REGL(0x10001c)#define rUMSTAT1 REGL(0x10401c)#define rUTXH0 REGB(0x100020)#define rUTXH1 REGB(0x104020)#define rURXH0 REGB(0x100024)#define rURXH1 REGB(0x104024)#define rUBRDIV0 REGL(0x100028)#define rUBRDIV1 REGL(0x104028)/*******************//* SIO Registers *//*******************/#define rSIOCON REGL(0x114000)#define rSIODAT REGL(0x114004)#define rSBRDR REGL(0x114008)#define rITVCNT REGL(0x11400c)#define rDCNTZ REGL(0x114010)/********************//* IIS Registers *//********************/#define rIISCON REGL(0x118000)#define rIISMOD REGL(0x118004)#define rIISPSR REGL(0x118008)#define rIISFCON REGL(0x11800c)#define rIISFIF REGW(0x118010)/**************************//* I/O Ports Registers *//**************************/#define rPCONA REGL(0x120000)#define rPDATA REGL(0x120004)#define rPCONB REGL(0x120008)#define rPDATB REGL(0x12000c)#define rPCONC REGL(0x120010)#define rPDATC REGL(0x120014)#define rPUPC REGL(0x120018)#define rPCOND REGL(0x12001c)#define rPDATD REGL(0x120020)#define rPUPD REGL(0x120024)#define rPCONE REGL(0x120028)#define rPDATE REGL(0x12002c)#define rPUPE REGL(0x120030)#define rPCONF REGL(0x120034)#define rPDATF REGL(0x120038)#define rPUPF REGL(0x12003c)#define rPCONG REGL(0x120040)#define rPDATG REGL(0x120044)#define rPUPG REGL(0x120048)#define rSPUCR REGL(0x12004c)#define rEXTINT REGL(0x120050)#define rEXTINTPND REGL(0x120054)/*********************************//* WatchDog Timers Registers *//*********************************/#define rWTCON REGL(0x130000)#define rWTDAT REGL(0x130004)#define rWTCNT REGL(0x130008)/*********************************//* A/D Converter Registers *//*********************************/#define rADCCON REGL(0x140000)#define rADCPSR REGL(0x140004)#define rADCDAT REGL(0x140008)/***************************//* PWM Timer Registers *//***************************/#define rTCFG0 REGL(0x150000)#define rTCFG1 REGL(0x150004)#define rTCON REGL(0x150008)#define rTCNTB0 REGL(0x15000c)#define rTCMPB0 REGL(0x150010)#define rTCNTO0 REGL(0x150014)#define rTCNTB1 REGL(0x150018)#define rTCMPB1 REGL(0x15001c)#define rTCNTO1 REGL(0x150020)#define rTCNTB2 REGL(0x150024)#define rTCMPB2 REGL(0x150028)#define rTCNTO2 REGL(0x15002c)#define rTCNTB3 REGL(0x150030)#define rTCMPB3 REGL(0x150034)#define rTCNTO3 REGL(0x150038)#define rTCNTB4 REGL(0x15003c)#define rTCMPB4 REGL(0x150040)#define rTCNTO4 REGL(0x150044)#define rTCNTB5 REGL(0x150048)#define rTCNTO5 REGL(0x15004c)/*********************//* IIC Registers *//*********************/#define rIICCON REGL(0x160000)#define rIICSTAT REGL(0x160004)#define rIICADD REGL(0x160008)#define rIICDS REGL(0x16000c)/*********************//* RTC Registers *//*********************/#define rRTCCON REGB(0x170040)#define rRTCALM REGB(0x170050)#define rALMSEC REGB(0x170054)#define rALMMIN REGB(0x170058)#define rALMHOUR REGB(0x17005c)#define rALMDAY REGB(0x170060)#define rALMMON REGB(0x170064)#define rALMYEAR REGB(0x170068)#define rRTCRST REGB(0x17006c)#define rBCDSEC REGB(0x170070)#define rBCDMIN REGB(0x170074)#define rBCDHOUR REGB(0x170078)#define rBCDDAY REGB(0x17007c)#define rBCDDATE REGB(0x170080)#define rBCDMON REGB(0x170084)#define rBCDYEAR REGB(0x170088)#define rTICINT REGB(0x17008c)/*********************************//* Clock & Power Registers *//*********************************/#define rPLLCON REGL(0x180000)#define rCLKCON REGL(0x180004)#define rCLKSLOW REGL(0x180008)#define rLOCKTIME REGL(0x18000c)/**************************************//* Interrupt Controller Registers *//**************************************/#define rINTCON REGL(0x200000)#define rINTPND REGL(0x200004)#define rINTMOD REGL(0x200008)#define rINTMSK REGL(0x20000c)#define rI_PSLV REGL(0x200010)#define rI_PMST REGL(0x200014)#define rI_CSLV REGL(0x200018)#define rI_CMST REGL(0x20001c)#define rI_ISPR REGL(0x200020)#define rI_ISPC REGL(0x200024)#define rF_ISPR REGL(0x200038)#define rF_ISPC REGL(0x20003c)/********************************//* LCD Controller Registers *//********************************/#define rLCDCON1 REGL(0x300000)#define rLCDCON2 REGL(0x300004)#define rLCDSADDR1 REGL(0x300008)#define rLCDSADDR2 REGL(0x30000c)#define rLCDSADDR3 REGL(0x300010)#define rREDLUT REGL(0x300014)#define rGREENLUT REGL(0x300018)#define rBLUELUT REGL(0x30001c)#define rDP1_2 REGL(0x300020)#define rDP4_7 REGL(0x300024)#define rDP3_5 REGL(0x300028)#define rDP2_3 REGL(0x30002c)#define rDP5_7 REGL(0x300030)#define rDP3_4 REGL(0x300034)#define rDP4_5 REGL(0x300038)#define rDP6_7 REGL(0x30003c)#define rLCDCON3 REGL(0x300040)#define rDITHMODE REGL(0x300044)/*********************//* DMA Registers *//*********************/#define rZDCON0 REGL(0x280000)#define rZDISRC0 REGL(0x280004)#define rZDIDES0 REGL(0x280008)#define rZDICNT0 REGL(0x28000c)#define rZDCSRC0 REGL(0x280010)#define rZDCDES0 REGL(0x280014)#define rZDCCNT0 REGL(0x280018)#define rZDCON1 REGL(0x280020)#define rZDISRC1 REGL(0x280024)#define rZDIDES1 REGL(0x280028)#define rZDICNT1 REGL(0x28002c)#define rZDCSRC1 REGL(0x280030)#define rZDCDES1 REGL(0x280034)#define rZDCCNT1 REGL(0x280038)#define rBDCON0 REGL(0x380000)#define rBDISRC0 REGL(0x380004)#define rBDIDES0 REGL(0x380008)#define rBDICNT0 REGL(0x38000c)#define rBDCSRC0 REGL(0x380010)#define rBDCDES0 REGL(0x380014)#define rBDCCNT0 REGL(0x380018)#define rBDCON1 REGL(0x380020)#define rBDISRC1 REGL(0x380024)#define rBDIDES1 REGL(0x380028)#define rBDICNT1 REGL(0x38002c)#define rBDCSRC1 REGL(0x380030)#define rBDCDES1 REGL(0x380034)#define rBDCCNT1 REGL(0x380038)#define CLEAR_PEND_INT(n) rI_ISPC = (1<<(n))#define CLEAR_PEND_ALL rI_ISPC = 0xFFFFFFFF#define CLEAR_PEND_FIQ(n) rF_ISPC = (1<<(n))#define INT_ENABLE(n) rINTMSK &= ~(1<<(n))#define INT_DISABLE(n) rINTMSK |= (1<<(n))#endif⌨️ 快捷键说明
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