da.tan.rpt

实现da转换功能

; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM1270T144C5ES    ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                     ; To                                                       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 84.72 MHz ( period = 11.803 ns )                    ; state.s3                                                 ; state.s1                                                 ; clk        ; clk      ; None                        ; None                      ; 11.239 ns               ;
; N/A                                     ; 85.12 MHz ( period = 11.748 ns )                    ; state.s2                                                 ; state.s1                                                 ; clk        ; clk      ; None                        ; None                      ; 11.184 ns               ;
; N/A                                     ; 86.46 MHz ( period = 11.566 ns )                    ; state.s1                                                 ; state.s1                                                 ; clk        ; clk      ; None                        ; None                      ; 11.002 ns               ;
; N/A                                     ; 89.67 MHz ( period = 11.152 ns )                    ; state.s3                                                 ; state.s3                                                 ; clk        ; clk      ; None                        ; None                      ; 10.588 ns               ;
; N/A                                     ; 91.15 MHz ( period = 10.971 ns )                    ; state.s3                                                 ; state.s0                                                 ; clk        ; clk      ; None                        ; None                      ; 10.407 ns               ;
; N/A                                     ; 91.67 MHz ( period = 10.909 ns )                    ; state.s2                                                 ; state.s3                                                 ; clk        ; clk      ; None                        ; None                      ; 10.345 ns               ;
; N/A                                     ; 91.73 MHz ( period = 10.901 ns )                    ; state.s3                                                 ; process5_367                                             ; clk        ; clk      ; None                        ; None                      ; 10.119 ns               ;
; N/A                                     ; 91.73 MHz ( period = 10.901 ns )                    ; state.s3                                                 ; process5_358                                             ; clk        ; clk      ; None                        ; None                      ; 10.119 ns               ;
; N/A                                     ; 91.73 MHz ( period = 10.901 ns )                    ; state.s3                                                 ; process5_349                                             ; clk        ; clk      ; None                        ; None                      ; 10.119 ns               ;
; N/A                                     ; 92.47 MHz ( period = 10.814 ns )                    ; process5_418                                             ; state.s3                                                 ; clk        ; clk      ; None                        ; None                      ; 10.468 ns               ;
; N/A                                     ; 93.21 MHz ( period = 10.728 ns )                    ; state.s2                                                 ; state.s0                                                 ; clk        ; clk      ; None                        ; None                      ; 10.164 ns               ;
; N/A                                     ; 93.83 MHz ( period = 10.658 ns )                    ; state.s2                                                 ; process5_367                                             ; clk        ; clk      ; None                        ; None                      ; 9.876 ns                ;
; N/A                                     ; 93.83 MHz ( period = 10.658 ns )                    ; state.s2                                                 ; process5_358                                             ; clk        ; clk      ; None                        ; None                      ; 9.876 ns                ;
; N/A                                     ; 93.83 MHz ( period = 10.658 ns )                    ; state.s2                                                 ; process5_349                                             ; clk        ; clk      ; None                        ; None                      ; 9.876 ns                ;
; N/A                                     ; 94.05 MHz ( period = 10.633 ns )                    ; process5_418                                             ; state.s0                                                 ; clk        ; clk      ; None                        ; None                      ; 10.287 ns               ;