daa.vhd

实现da转换功能

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY daa IS
	PORT
	(
		clk                 : IN	STD_LOGIC;
		clk_out             : out	STD_LOGIC;
		pdb1,pdb2,pdb3		: OUT	STD_LOGIC;
		data1,data2	        : out	STD_LOGIC_VECTOR(7 DOWNTO 0);
		ins                 : out   STD_LOGIC_VECTOR(2 DOWNTO 0)
		--led                 : out   STD_LOGIC_VECTOR(1 DOWNTO 0)
	);
END daa;

ARCHITECTURE a OF daa IS 
------------------------------------------------------------------------
	
	type state_type  is (s0,s1,s2,s3);
	signal state,next_state :state_type;
	SIGNAL cnt0              : STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL cnt              : STD_LOGIC_VECTOR(9 DOWNTO 0);
	SIGNAL cnt1             : STD_LOGIC_VECTOR(8 DOWNTO 0);
	signal counter1,counter2          : STD_LOGIC_VECTOR(7 DOWNTO 0);
	signal sign,clk0,clk1,clk2             : std_logic;

BEGIN
	
--****************************************************************
	PROCESS(clk)
	BEGIN 
	IF(rising_edge(clk))THEN
	IF cnt0="111" THEN 
		cnt0<="000";
		clk0<=not(clk0);
	ELSE cnt0<=cnt0+1;
	END IF;
	END IF;
	END PROCESS;
	
	PROCESS(clk)
	BEGIN 
	IF(rising_edge(clk))THEN
	IF cnt="1111111111" THEN 
		cnt<="0000000000";
		clk1<=not(clk1);
	ELSE cnt<=cnt+1;
	END IF;
	END IF;
	END PROCESS;
	----------------------------------------
	PROCESS(clk)
	BEGIN 
	IF(rising_edge(clk))THEN
	IF cnt1="111111111" THEN 
		cnt1<="000000000";
		clk2<=not(clk2);
	ELSE cnt1<=cnt1+1;
	END IF;
	END IF;
	END PROCESS;
	-----------------------------------------
	pdb1<='0';
	pdb2<='0';
	pdb3<='1';
	ins<="010";
	--********************************************
	
	process(state)
	begin
	case state is
	when s0 =>  next_state<=s1;
	when s1 => if counter1="11111111" then
				next_state<=s2;
				else 
				next_state<=s1;
				end if;
	when s2=>  next_state<= s3;
	when s3=>  if counter2="00000000" then
				next_state<=s0;
				else 
				next_state<= s3;
				end if;
	end case;
	end process;
	
	process(clk0)
	begin
	IF(rising_edge(clk0))THEN
	state<=next_state;
	end if;
	end process;
	
	process(state)
	begin
	case state is
	when s0 => counter1<="00000000";
			   counter2<="00000000";
				sign<='0';
				--led<="00";
	when s1 => IF(rising_edge(clk1))THEN 
			    counter1<=counter1+1;
			   end if;
			  -- led<="01";
	when s2 => counter2<="11111111";
			    sign<='1';
			   -- led<="10";
	when s3 => IF(rising_edge(clk2))THEN 
			    counter2<=counter2-1;
			   end if;
			    --led<="11";
	end case;
	end process;
	
	process(sign)
	begin
	IF sign='0' THEN
	clk_out<=clk1;
	data1<=counter1;
	data2<=counter1;
	else
	clk_out<=clk2;
	data1<=counter2;
	data2<=counter2;
	end if;
	end process;
				
END a;