📄 da.fit.rpt
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+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 0.92) ; Number of LABs (Total = 13) ;
+------------------------------------+------------------------------+
; 1 Clock ; 10 ;
; 1 Clock enable ; 1 ;
; 2 Clock enables ; 1 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 7.00) ; Number of LABs (Total = 13) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 2 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 2 ;
; 10 ; 6 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 5.54) ; Number of LABs (Total = 13) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 3 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 2 ;
; 9 ; 2 ;
; 10 ; 2 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 7.62) ; Number of LABs (Total = 13) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 2 ;
; 3 ; 2 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 11 ; 1 ;
; 12 ; 1 ;
; 13 ; 2 ;
; 14 ; 1 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Sun Aug 14 17:08:30 2005
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off da -c da
Info: Selected device EPM1270T144C5ES for design "da"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM570T144C5 is compatible
Info: Device EPM1270T144C5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Automatically promoted some destinations of signal "clk1" to use Global clock
Info: Destination "clk1" may be non-global or may not use global clock
Info: Destination "clk_out~10" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "clk2" to use Global clock
Info: Destination "clk2" may be non-global or may not use global clock
Info: Destination "clk_out~10" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "clk0" to use Global clock
Info: Destination "clk0" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 0 seconds
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to pin delay of 10.229 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y6; Fanout = 1; REG Node = 'process5_358'
Info: 2: + IC(0.924 ns) + CELL(0.932 ns) = 1.856 ns; Loc. = LAB_X14_Y6; Fanout = 2; COMB Node = 'Select~319'
Info: 3: + IC(0.278 ns) + CELL(0.932 ns) = 3.066 ns; Loc. = LAB_X14_Y6; Fanout = 6; COMB Node = 'counter2[6]'
Info: 4: + IC(1.436 ns) + CELL(0.932 ns) = 5.434 ns; Loc. = LAB_X14_Y7; Fanout = 2; COMB Node = 'data1~65'
Info: 5: + IC(2.473 ns) + CELL(2.322 ns) = 10.229 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'data1[6]'
Info: Total cell delay = 5.118 ns ( 50.03 % )
Info: Total interconnect delay = 5.111 ns ( 49.97 % )
Info: Estimated interconnect usage is 2% of the available device resources
Info: Fitter placement operations ending: elapsed time = 1 seconds
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time = 0 seconds
Info: Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and/or routability requirements required full optimization
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sun Aug 14 17:08:41 2005
Info: Elapsed time: 00:00:12
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