da_0.vhd

实现da转换功能

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY da_0 IS
	PORT
	(
		clk                 : IN	STD_LOGIC;
		clk_out                : buffer	STD_LOGIC;
		pdb1,pdb2,pdb3		: OUT	STD_LOGIC;
		data1,data2	            : out	STD_LOGIC_VECTOR(7 DOWNTO 0);
		ins                 : out   STD_LOGIC_VECTOR(2 DOWNTO 0)
	);
END da_0;

ARCHITECTURE a OF da_0 IS 
------------------------------------------------------------------------
	
	type state_type  is (s0,s1,s2,s3);
	signal state,next_state :state_type;
	SIGNAL cnt              : STD_LOGIC_VECTOR(19 DOWNTO 0);
	SIGNAL cnt1             : STD_LOGIC_VECTOR(18 DOWNTO 0);
	signal counter1,counter2          : STD_LOGIC_VECTOR(7 DOWNTO 0);
	signal sign,clk1,clk2             : std_logic;

BEGIN
	
--****************************************************************
	PROCESS(clk)
	BEGIN 
	IF(rising_edge(clk))THEN
	IF cnt="11111111111111111111" THEN 
		cnt<="00000000000000000000";
		clk1<=not(clk1);
	ELSE cnt<=cnt+1;
	END IF;
	END IF;
	END PROCESS;
	----------------------------------------
	PROCESS(clk)
	BEGIN 
	IF(rising_edge(clk))THEN
	IF cnt1="1111111111111111111" THEN 
		cnt1<="0000000000000000000";
		clk2<=not(clk2);
	ELSE cnt<=cnt+1;
	END IF;
	END IF;
	END PROCESS;
	-----------------------------------------
	pdb1<='0';
	pdb2<='0';
	pdb3<='1';
	ins<="010";
	--********************************************
	
	process(state)
	begin
	case state is
	when s0 => next_state<=s1;
	when s1 => if counter1="11111111" then
				next_state<=s2;
				end if;
	when s2=>  next_state<= s3;
	when s3=>  if counter2="00000000" then
				next_state<=s0;
				end if;
	end case;
	end process;
	
	process(clk)
	begin
	IF(rising_edge(clk))THEN
	state<=next_state;
	end if;
	end process;
	
	process(state)
	begin
	case state is
	when s0 => counter1<="00000000";
				sign<='0';
	when s1 => IF(rising_edge(clk1))THEN 
			    counter1<=counter1+1;
			   end if;
	when s2 => counter2<="11111111";
			    sign<='1';
	when s3 => IF(rising_edge(clk2))THEN 
			    counter2<=counter2-1;
			   end if;
	end case;
	end process;
	
	process(sign)
	begin
	IF sign='0' THEN
	clk_out<=clk1;
	data1<=counter1;
	data2<=counter1;
	else
	clk_out<=clk2;
	data1<=counter2;
	data2<=counter2;
	end if;
	end process;
				
END a;