a2d.tan.qmsg

将AD转换得到的八位数据存入RAM

{ "Info" "ITDB_FULL_TCO_RESULT" "clk ld\[4\] t_addata\[4\] 10.759 ns register " "Info: tco from clock \"clk\" to destination pin \"ld\[4\]\" through register \"t_addata\[4\]\" is 10.759 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 101 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 101; CLK Node = 'clk'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns t_addata\[4\] 2 REG LC_X10_Y5_N9 3 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y5_N9; Fanout = 3; REG Node = 't_addata\[4\]'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk t_addata[4] } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk t_addata[4] } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout t_addata[4] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.564 ns + Longest register pin " "Info: + Longest register to pin delay is 6.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns t_addata\[4\] 1 REG LC_X10_Y5_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y5_N9; Fanout = 3; REG Node = 't_addata\[4\]'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { t_addata[4] } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.242 ns) + CELL(2.322 ns) 6.564 ns ld\[4\] 2 PIN PIN_76 0 " "Info: 2: + IC(4.242 ns) + CELL(2.322 ns) = 6.564 ns; Loc. = PIN_76; Fanout = 0; PIN Node = 'ld\[4\]'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.564 ns" { t_addata[4] ld[4] } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 35.37 % ) " "Info: Total cell delay = 2.322 ns ( 35.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.242 ns ( 64.63 % ) " "Info: Total interconnect delay = 4.242 ns ( 64.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.564 ns" { t_addata[4] ld[4] } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "6.564 ns" { t_addata[4] ld[4] } { 0.000ns 4.242ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk t_addata[4] } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout t_addata[4] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.564 ns" { t_addata[4] ld[4] } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "6.564 ns" { t_addata[4] ld[4] } { 0.000ns 4.242ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "t_addata\[2\] datain\[2\] clk -1.311 ns register " "Info: th for register \"t_addata\[2\]\" (data pin = \"datain\[2\]\", clock pin = \"clk\") is -1.311 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 101 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 101; CLK Node = 'clk'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns t_addata\[2\] 2 REG LC_X6_Y5_N2 2 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X6_Y5_N2; Fanout = 2; REG Node = 't_addata\[2\]'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk t_addata[2] } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk t_addata[2] } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout t_addata[2] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.351 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.351 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns datain\[2\] 1 PIN PIN_3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_3; Fanout = 1; PIN Node = 'datain\[2\]'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { datain[2] } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.939 ns) + CELL(0.280 ns) 5.351 ns t_addata\[2\] 2 REG LC_X6_Y5_N2 2 " "Info: 2: + IC(3.939 ns) + CELL(0.280 ns) = 5.351 ns; Loc. = LC_X6_Y5_N2; Fanout = 2; REG Node = 't_addata\[2\]'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.219 ns" { datain[2] t_addata[2] } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 26.39 % ) " "Info: Total cell delay = 1.412 ns ( 26.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.939 ns ( 73.61 % ) " "Info: Total interconnect delay = 3.939 ns ( 73.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.351 ns" { datain[2] t_addata[2] } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "5.351 ns" { datain[2] datain[2]~combout t_addata[2] } { 0.000ns 0.000ns 3.939ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk t_addata[2] } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout t_addata[2] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.351 ns" { datain[2] t_addata[2] } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "5.351 ns" { datain[2] datain[2]~combout t_addata[2] } { 0.000ns 0.000ns 3.939ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "101 " "Info: Allocated 101 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 30 06:56:02 2008 " "Info: Processing ended: Wed Apr 30 06:56:02 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}