a2d.tan.qmsg

将AD转换得到的八位数据存入RAM

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 7 -1 0 } } { "f:/70/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count1\[8\] register t_ramsi 57.08 MHz 17.52 ns Internal " "Info: Clock \"clk\" has Internal fmax of 57.08 MHz between source register \"count1\[8\]\" and destination register \"t_ramsi\" (period= 17.52 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.811 ns + Longest register register " "Info: + Longest register to register delay is 16.811 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count1\[8\] 1 REG LC_X9_Y9_N9 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y9_N9; Fanout = 11; REG Node = 'count1\[8\]'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { count1[8] } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.860 ns) + CELL(0.200 ns) 3.060 ns LessThan5~268 2 COMB LC_X10_Y5_N1 7 " "Info: 2: + IC(2.860 ns) + CELL(0.200 ns) = 3.060 ns; Loc. = LC_X10_Y5_N1; Fanout = 7; COMB Node = 'LessThan5~268'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.060 ns" { count1[8] LessThan5~268 } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.149 ns) + CELL(0.914 ns) 7.123 ns LessThan6~220 3 COMB LC_X10_Y7_N3 14 " "Info: 3: + IC(3.149 ns) + CELL(0.914 ns) = 7.123 ns; Loc. = LC_X10_Y7_N3; Fanout = 14; COMB Node = 'LessThan6~220'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.063 ns" { LessThan5~268 LessThan6~220 } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.511 ns) 10.234 ns comb~3761 4 COMB LC_X8_Y8_N5 1 " "Info: 4: + IC(2.600 ns) + CELL(0.511 ns) = 10.234 ns; Loc. = LC_X8_Y8_N5; Fanout = 1; COMB Node = 'comb~3761'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { LessThan6~220 comb~3761 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.773 ns) + CELL(0.200 ns) 12.207 ns comb~3763 5 COMB LC_X9_Y8_N3 1 " "Info: 5: + IC(1.773 ns) + CELL(0.200 ns) = 12.207 ns; Loc. = LC_X9_Y8_N3; Fanout = 1; COMB Node = 'comb~3763'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.973 ns" { comb~3761 comb~3763 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.721 ns) + CELL(0.200 ns) 13.128 ns comb~21 6 COMB LC_X9_Y8_N9 2 " "Info: 6: + IC(0.721 ns) + CELL(0.200 ns) = 13.128 ns; Loc. = LC_X9_Y8_N9; Fanout = 2; COMB Node = 'comb~21'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.921 ns" { comb~3763 comb~21 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.440 ns) + CELL(1.243 ns) 16.811 ns t_ramsi 7 REG LC_X7_Y5_N3 1 " "Info: 7: + IC(2.440 ns) + CELL(1.243 ns) = 16.811 ns; Loc. = LC_X7_Y5_N3; Fanout = 1; REG Node = 't_ramsi'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.683 ns" { comb~21 t_ramsi } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.268 ns ( 19.44 % ) " "Info: Total cell delay = 3.268 ns ( 19.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.543 ns ( 80.56 % ) " "Info: Total interconnect delay = 13.543 ns ( 80.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "16.811 ns" { count1[8] LessThan5~268 LessThan6~220 comb~3761 comb~3763 comb~21 t_ramsi } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "16.811 ns" { count1[8] LessThan5~268 LessThan6~220 comb~3761 comb~3763 comb~21 t_ramsi } { 0.000ns 2.860ns 3.149ns 2.600ns 1.773ns 0.721ns 2.440ns } { 0.000ns 0.200ns 0.914ns 0.511ns 0.200ns 0.200ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 101 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 101; CLK Node = 'clk'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns t_ramsi 2 REG LC_X7_Y5_N3 1 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X7_Y5_N3; Fanout = 1; REG Node = 't_ramsi'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk t_ramsi } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk t_ramsi } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout t_ramsi } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 101 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 101; CLK Node = 'clk'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns count1\[8\] 2 REG LC_X9_Y9_N9 11 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X9_Y9_N9; Fanout = 11; REG Node = 'count1\[8\]'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk count1[8] } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk count1[8] } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout count1[8] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk t_ramsi } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout t_ramsi } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk count1[8] } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout count1[8] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "16.811 ns" { count1[8] LessThan5~268 LessThan6~220 comb~3761 comb~3763 comb~21 t_ramsi } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "16.811 ns" { count1[8] LessThan5~268 LessThan6~220 comb~3761 comb~3763 comb~21 t_ramsi } { 0.000ns 2.860ns 3.149ns 2.600ns 1.773ns 0.721ns 2.440ns } { 0.000ns 0.200ns 0.914ns 0.511ns 0.200ns 0.200ns 1.243ns } "" } } { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk t_ramsi } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout t_ramsi } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk count1[8] } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout count1[8] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "t_ramso\[4\] sw0 clk 5.409 ns register " "Info: tsu for register \"t_ramso\[4\]\" (data pin = \"sw0\", clock pin = \"clk\") is 5.409 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.895 ns + Longest pin register " "Info: + Longest pin to register delay is 8.895 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sw0 1 PIN PIN_134 61 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_134; Fanout = 61; PIN Node = 'sw0'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sw0 } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.926 ns) + CELL(0.740 ns) 4.798 ns Decoder0~147 2 COMB LC_X7_Y7_N9 1 " "Info: 2: + IC(2.926 ns) + CELL(0.740 ns) = 4.798 ns; Loc. = LC_X7_Y7_N9; Fanout = 1; COMB Node = 'Decoder0~147'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.666 ns" { sw0 Decoder0~147 } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 269 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.711 ns) + CELL(0.200 ns) 5.709 ns Decoder0~148 3 COMB LC_X7_Y7_N4 8 " "Info: 3: + IC(0.711 ns) + CELL(0.200 ns) = 5.709 ns; Loc. = LC_X7_Y7_N4; Fanout = 8; COMB Node = 'Decoder0~148'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.911 ns" { Decoder0~147 Decoder0~148 } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 269 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.248 ns) + CELL(0.200 ns) 7.157 ns Decoder0~151 4 COMB LC_X7_Y7_N0 1 " "Info: 4: + IC(1.248 ns) + CELL(0.200 ns) = 7.157 ns; Loc. = LC_X7_Y7_N0; Fanout = 1; COMB Node = 'Decoder0~151'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.448 ns" { Decoder0~148 Decoder0~151 } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 269 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.147 ns) + CELL(0.591 ns) 8.895 ns t_ramso\[4\] 5 REG LC_X8_Y7_N5 2 " "Info: 5: + IC(1.147 ns) + CELL(0.591 ns) = 8.895 ns; Loc. = LC_X8_Y7_N5; Fanout = 2; REG Node = 't_ramso\[4\]'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.738 ns" { Decoder0~151 t_ramso[4] } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.863 ns ( 32.19 % ) " "Info: Total cell delay = 2.863 ns ( 32.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.032 ns ( 67.81 % ) " "Info: Total interconnect delay = 6.032 ns ( 67.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.895 ns" { sw0 Decoder0~147 Decoder0~148 Decoder0~151 t_ramso[4] } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "8.895 ns" { sw0 sw0~combout Decoder0~147 Decoder0~148 Decoder0~151 t_ramso[4] } { 0.000ns 0.000ns 2.926ns 0.711ns 1.248ns 1.147ns } { 0.000ns 1.132ns 0.740ns 0.200ns 0.200ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 101 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 101; CLK Node = 'clk'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns t_ramso\[4\] 2 REG LC_X8_Y7_N5 2 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X8_Y7_N5; Fanout = 2; REG Node = 't_ramso\[4\]'" {  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk t_ramso[4] } "NODE_NAME" } } { "a2d.vhd" "" { Text "F:/电子设计/ram_da/a2d.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk t_ramso[4] } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout t_ramso[4] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.895 ns" { sw0 Decoder0~147 Decoder0~148 Decoder0~151 t_ramso[4] } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "8.895 ns" { sw0 sw0~combout Decoder0~147 Decoder0~148 Decoder0~151 t_ramso[4] } { 0.000ns 0.000ns 2.926ns 0.711ns 1.248ns 1.147ns } { 0.000ns 1.132ns 0.740ns 0.200ns 0.200ns 0.591ns } "" } } { "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk t_ramso[4] } "NODE_NAME" } } { "f:/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout t_ramso[4] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}