📄 a2d.sim.rpt
字号:
; |a2d|Add1~194 ; |a2d|Add1~195COUT1 ; cout1 ;
; |a2d|Add1~196 ; |a2d|Add1~197COUT1 ; cout1 ;
; |a2d|Add1~200 ; |a2d|Add1~201COUT1 ; cout1 ;
; |a2d|Add1~202 ; |a2d|Add1~203COUT1 ; cout1 ;
; |a2d|Add1~204 ; |a2d|Add1~205 ; cout0 ;
; |a2d|Add1~206 ; |a2d|Add1~207 ; cout0 ;
; |a2d|Add1~208 ; |a2d|Add1~209 ; cout0 ;
; |a2d|Add1~210 ; |a2d|Add1~211 ; cout0 ;
; |a2d|Add3~117 ; |a2d|Add3~117 ; combout ;
; |a2d|count2[5] ; |a2d|Equal1~39 ; combout ;
; |a2d|count2[5] ; |a2d|count2[5] ; regout ;
; |a2d|comb~3620 ; |a2d|comb~3620 ; combout ;
; |a2d|Equal1~40 ; |a2d|Equal1~40 ; combout ;
; |a2d|count2[5]~822 ; |a2d|count2[5]~822 ; combout ;
; |a2d|Add3~119 ; |a2d|Add3~119 ; combout ;
; |a2d|Add3~119 ; |a2d|Add3~120 ; cout0 ;
; |a2d|Add3~119 ; |a2d|Add3~120COUT1 ; cout1 ;
; |a2d|Add3~121 ; |a2d|Add3~121 ; combout ;
; |a2d|Add3~121 ; |a2d|Add3~122 ; cout0 ;
; |a2d|Add3~121 ; |a2d|Add3~122COUT1 ; cout1 ;
; |a2d|Add3~123 ; |a2d|Add3~123 ; combout ;
; |a2d|Add3~123 ; |a2d|Add3~124 ; cout0 ;
; |a2d|Add3~123 ; |a2d|Add3~124COUT1 ; cout1 ;
; |a2d|Add3~125 ; |a2d|Add3~125 ; combout ;
; |a2d|Add3~125 ; |a2d|Add3~126 ; cout ;
; |a2d|Add3~127 ; |a2d|Add3~127 ; combout ;
; |a2d|Add3~127 ; |a2d|Add3~128 ; cout0 ;
; |a2d|Add3~127 ; |a2d|Add3~128COUT1 ; cout1 ;
; |a2d|Add1~216 ; |a2d|Add1~217 ; cout0 ;
; |a2d|Add3~129 ; |a2d|Add3~129 ; combout ;
; |a2d|Add3~129 ; |a2d|Add3~130 ; cout0 ;
; |a2d|Add3~129 ; |a2d|Add3~130COUT1 ; cout1 ;
; |a2d|Add3~131 ; |a2d|Add3~131 ; combout ;
; |a2d|Add3~131 ; |a2d|Add3~132 ; cout0 ;
; |a2d|Add3~131 ; |a2d|Add3~132COUT1 ; cout1 ;
; |a2d|count3[0]~1394 ; |a2d|count3[0]~1394 ; combout ;
; |a2d|count3[0]~1395 ; |a2d|count3[0]~1395 ; combout ;
; |a2d|count3[0]~1401 ; |a2d|count3[0]~1401 ; combout ;
; |a2d|count3[0]~1402 ; |a2d|count3[0]~1402 ; combout ;
; |a2d|count3[0]~1403 ; |a2d|count3[0]~1403 ; combout ;
; |a2d|t_ramdata[5] ; |a2d|t_ramdata[5] ; regout ;
; |a2d|t_ramdata[7] ; |a2d|t_ramdata[7] ; regout ;
; |a2d|comb~3622 ; |a2d|comb~3622 ; combout ;
; |a2d|t_ramaddr[14] ; |a2d|t_ramaddr[14] ; regout ;
; |a2d|t_ramaddr[14] ; |a2d|t_ramaddr[14]~1016 ; cout0 ;
; |a2d|t_ramaddr[14] ; |a2d|t_ramaddr[14]~1016COUT1 ; cout1 ;
; |a2d|t_ramaddr[6] ; |a2d|t_ramaddr[6] ; regout ;
; |a2d|t_ramaddr[6] ; |a2d|t_ramaddr[6]~1017 ; cout0 ;
; |a2d|t_ramaddr[6] ; |a2d|t_ramaddr[6]~1017COUT1 ; cout1 ;
; |a2d|LessThan18~72 ; |a2d|LessThan18~72 ; combout ;
; |a2d|comb~3623 ; |a2d|comb~3623 ; combout ;
; |a2d|t_ramaddr[13] ; |a2d|t_ramaddr[13] ; regout ;
; |a2d|t_ramaddr[13] ; |a2d|t_ramaddr[13]~1018 ; cout0 ;
; |a2d|t_ramaddr[13] ; |a2d|t_ramaddr[13]~1018COUT1 ; cout1 ;
; |a2d|t_ramaddr[5] ; |a2d|t_ramaddr[5] ; regout ;
; |a2d|t_ramaddr[5] ; |a2d|t_ramaddr[5]~1019 ; cout0 ;
; |a2d|t_ramaddr[5] ; |a2d|t_ramaddr[5]~1019COUT1 ; cout1 ;
; |a2d|comb~3624 ; |a2d|comb~3624 ; combout ;
; |a2d|t_ramaddr[12] ; |a2d|t_ramaddr[12] ; regout ;
; |a2d|t_ramaddr[12] ; |a2d|t_ramaddr[12]~1020 ; cout ;
; |a2d|t_ramaddr[4] ; |a2d|t_ramaddr[4] ; regout ;
; |a2d|t_ramaddr[4] ; |a2d|t_ramaddr[4]~1021 ; cout0 ;
; |a2d|t_ramaddr[4] ; |a2d|t_ramaddr[4]~1021COUT1 ; cout1 ;
; |a2d|comb~3625 ; |a2d|comb~3625 ; combout ;
; |a2d|t_ramaddr[15] ; |a2d|t_ramaddr[15] ; regout ;
; |a2d|t_ramaddr[7] ; |a2d|t_ramaddr[7] ; regout ;
; |a2d|t_ramaddr[7] ; |a2d|t_ramaddr[7]~1023 ; cout ;
; |a2d|comb~3626 ; |a2d|comb~3626 ; combout ;
; |a2d|t_ramaddr[9] ; |a2d|t_ramaddr[9]~1024 ; cout0 ;
; |a2d|t_ramaddr[9] ; |a2d|t_ramaddr[9]~1024COUT1 ; cout1 ;
; |a2d|comb~3627 ; |a2d|comb~3627 ; combout ;
; |a2d|t_ramaddr[10] ; |a2d|t_ramaddr[10]~1026 ; cout0 ;
; |a2d|t_ramaddr[10] ; |a2d|t_ramaddr[10]~1026COUT1 ; cout1 ;
; |a2d|comb~3628 ; |a2d|comb~3628 ; combout ;
; |a2d|t_ramaddr[8] ; |a2d|t_ramaddr[8]~1028 ; cout0 ;
; |a2d|t_ramaddr[8] ; |a2d|t_ramaddr[8]~1028COUT1 ; cout1 ;
; |a2d|comb~3629 ; |a2d|comb~3629 ; combout ;
; |a2d|t_ramaddr[11] ; |a2d|t_ramaddr[11] ; regout ;
; |a2d|t_ramaddr[11] ; |a2d|t_ramaddr[11]~1030 ; cout0 ;
; |a2d|t_ramaddr[11] ; |a2d|t_ramaddr[11]~1030COUT1 ; cout1 ;
; |a2d|t_ramaddr[3] ; |a2d|t_ramaddr[3] ; regout ;
; |a2d|t_ramaddr[3] ; |a2d|t_ramaddr[3]~1031 ; cout0 ;
; |a2d|comb~3630 ; |a2d|comb~3630 ; combout ;
; |a2d|comb~3631 ; |a2d|comb~3631 ; combout ;
; |a2d|t_addata[6] ; |a2d|t_addata[6] ; regout ;
; |a2d|t_addata[5] ; |a2d|t_ramdata~3447 ; combout ;
; |a2d|t_addata[5] ; |a2d|t_addata[5] ; regout ;
; |a2d|t_ramdata~3448 ; |a2d|t_ramdata~3448 ; combout ;
; |a2d|t_addata[4] ; |a2d|t_addata[4] ; regout ;
; |a2d|t_addata[7] ; |a2d|t_ramdata~3451 ; combout ;
; |a2d|t_addata[7] ; |a2d|t_addata[7] ; regout ;
; |a2d|t_ramdata~3452 ; |a2d|t_ramdata~3452 ; combout ;
; |a2d|t_addata[1] ; |a2d|t_addata[1] ; regout ;
; |a2d|t_addata[2] ; |a2d|t_addata[2] ; regout ;
; |a2d|t_addata[0] ; |a2d|t_addata[0] ; regout ;
; |a2d|t_addata[3] ; |a2d|t_addata[3] ; regout ;
; |a2d|comb~3636 ; |a2d|comb~3636 ; combout ;
; |a2d|comb~3637 ; |a2d|comb~3637 ; combout ;
; |a2d|Decoder0~141 ; |a2d|Decoder0~141 ; combout ;
; |a2d|ram_part_addr~3714 ; |a2d|ram_part_addr~3714 ; combout ;
; |a2d|ram_part_addr~3715 ; |a2d|ram_part_addr~3715 ; combout ;
; |a2d|ram_part_addr~3716 ; |a2d|ram_part_addr~3716 ; combout ;
; |a2d|ram_part_addr~3717 ; |a2d|ram_part_addr~3717 ; combout ;
; |a2d|ram_part_addr~3718 ; |a2d|ram_part_addr~3718 ; combout ;
; |a2d|ram_part_addr~3719 ; |a2d|ram_part_addr~3719 ; combout ;
; |a2d|ram_part_addr~3721 ; |a2d|ram_part_addr~3721 ; combout ;
; |a2d|t_dadata[14]~482 ; |a2d|t_dadata[14]~482 ; combout ;
; |a2d|t_sck~1005 ; |a2d|t_sck~1005 ; combout ;
; |a2d|ram_part_addr[0]~3724 ; |a2d|ram_part_addr[0]~3724 ; combout ;
; |a2d|ram_part_addr[2]~3733 ; |a2d|ram_part_addr[2]~3733 ; combout ;
; |a2d|t_ramso[6] ; |a2d|t_ramso[6] ; regout ;
; |a2d|t_ramso[5] ; |a2d|t_ramso[5] ; regout ;
; |a2d|t_ramso[4] ; |a2d|t_ramso[4] ; regout ;
; |a2d|t_ramso[7] ; |a2d|t_ramso[7] ; regout ;
; |a2d|t_ramso[2] ; |a2d|t_ramso[2] ; regout ;
; |a2d|t_ramso[1] ; |a2d|t_ramso[1] ; regout ;
; |a2d|t_ramso[0] ; |a2d|t_ramso[0] ; regout ;
; |a2d|t_ramso[3] ; |a2d|t_ramso[3] ; regout ;
; |a2d|t_ramdata[3]~3461 ; |a2d|t_ramdata[3]~3461 ; combout ;
; |a2d|LessThan17~86 ; |a2d|LessThan17~86 ; combout ;
; |a2d|comb~3645 ; |a2d|comb~3645 ; combout ;
; |a2d|comb~3651 ; |a2d|comb~3651 ; combout ;
; |a2d|t_ramaddr[10]~1032 ; |a2d|t_ramaddr[10]~1032 ; combout ;
; |a2d|t_ramaddr[10]~1033 ; |a2d|t_ramaddr[10]~1033 ; combout ;
; |a2d|t_ramaddr[10]~1034 ; |a2d|t_ramaddr[10]~1034 ; combout ;
; |a2d|t_ramaddr[10]~1035 ; |a2d|t_ramaddr[10]~1035 ; combout ;
; |a2d|t_ramaddr[10]~1036 ; |a2d|t_ramaddr[10]~1036 ; combout ;
; |a2d|t_ramaddr[10]~1037 ; |a2d|t_ramaddr[10]~1037 ; combout ;
; |a2d|Decoder0~143 ; |a2d|Decoder0~143 ; combout ;
; |a2d|Decoder0~144 ; |a2d|Decoder0~144 ; combout ;
; |a2d|Decoder0~145 ; |a2d|Decoder0~145 ; combout ;
; |a2d|Decoder0~146 ; |a2d|Decoder0~146 ; combout ;
; |a2d|Decoder0~147 ; |a2d|Decoder0~147 ; combout ;
; |a2d|Decoder0~148 ; |a2d|Decoder0~148 ; combout ;
; |a2d|Decoder0~149 ; |a2d|Decoder0~149 ; combout ;
; |a2d|Decoder0~150 ; |a2d|Decoder0~150 ; combout ;
; |a2d|Decoder0~151 ; |a2d|Decoder0~151 ; combout ;
; |a2d|sw0 ; |a2d|sw0 ; combout ;
; |a2d|datain[0] ; |a2d|datain[0] ; combout ;
; |a2d|datain[1] ; |a2d|datain[1] ; combout ;
; |a2d|datain[2] ; |a2d|datain[2] ; combout ;
; |a2d|datain[3] ; |a2d|datain[3] ; combout ;
; |a2d|datain[4] ; |a2d|datain[4] ; combout ;
; |a2d|datain[5] ; |a2d|datain[5] ; combout ;
; |a2d|datain[6] ; |a2d|datain[6] ; combout ;
; |a2d|datain[7] ; |a2d|datain[7] ; combout ;
; |a2d|ramso ; |a2d|ramso ; combout ;
; |a2d|ld[0] ; |a2d|ld[0] ; padio ;
; |a2d|ld[1] ; |a2d|ld[1] ; padio ;
; |a2d|ld[2] ; |a2d|ld[2] ; padio ;
; |a2d|ld[3] ; |a2d|ld[3] ; padio ;
; |a2d|ld[4] ; |a2d|ld[4] ; padio ;
; |a2d|ld[5] ; |a2d|ld[5] ; padio ;
; |a2d|ld[6] ; |a2d|ld[6] ; padio ;
; |a2d|ld[7] ; |a2d|ld[7] ; padio ;
; |a2d|dacs ; |a2d|dacs ; padio ;
; |a2d|dasck ; |a2d|dasck ; padio ;
; |a2d|dadin ; |a2d|dadin ; padio ;
+----------------------------+------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Sun Apr 27 23:02:56 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off a2d -c a2d
Info: Using vector source file "E:/08design/works/a2d5/a2d.vwf"
Info: Inverted registers were found during simulation
Info: Register: |a2d|t_adcs
Info: Register: |a2d|t_rd
Info: Register: |a2d|t_ramcs
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 50.36 %
Info: Number of transitions in simulation is 679698
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Allocated 90 megabytes of memory during processing
Info: Processing ended: Sun Apr 27 23:03:18 2008
Info: Elapsed time: 00:00:22
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