a2d(digitaldeng).txt

将AD转换得到的八位数据存入RAM

-- tlc0820ac ---a/d转换
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all;
entity a2d is
port(clk :in std_logic;--输入时钟信号50MHz
	 rst : in std_logic;  --复位
	
--	 mode :out std_logic;  --0820模式，1为写0为读，悬空相当于低
	 cs : out std_logic;
	 rd : out std_logic;
	 int : in std_logic;
	 datain : in std_logic_vector(7 downto 0);
--	 dataout : out std_logic_vector(7 downto 0)
--数码管
	cat : out std_logic_vector(5 downto 0);  --6个数码管
	segout : out std_logic_vector(6 downto 0);  --7段数码管
	ld: out std_logic_vector(7 downto 0)   --ld显示采样的数字值
	);
end a2d;
architecture aa of a2d is
signal t_rd, t_cs : std_logic;
signal count: integer range 0 to 154; --total采样间隔为50+2600=3100ns
signal t_int: integer range 0 to 15;		--350ns 肯定够int变为高了
signal t_data :std_logic_vector(7 downto 0);
signal count : std_logic_vector(7 downto 0);
signal val : std_logic_vector(19 downto 0);
component dl
port(
	clk : in std_logic;
--	rst : in std_logic;
	cat : out std_logic_vector(5 downto 0);  --6个数码管
	segout : out std_logic_vector(6 downto 0);  --7段数码管
	datain6 : in std_logic_vector(3 downto 0);  --待显示的最高位
	datain5 : in std_logic_vector(3 downto 0);
	datain4 : in std_logic_vector(3 downto 0);
	datain3 : in std_logic_vector(3 downto 0);
	datain2 : in std_logic_vector(3 downto 0);
	datain1 : in std_logic_vector(3 downto 0)
	);
end component;

begin
process(clk,int,rst)
begin

--异步复位
if rst='1' then
	count <= 0;
	t_cs <= '1';
	t_rd <= '1';
	t_data <= "00000000";

--计数器
	elsif(clk'event and clk='1') then
		if count=154 then
			count<=0;
		else 
			count<=count+1;
		end if;

		--时序控制
		if count < 3 then
			t_cs<='1';
			t_rd<='1';
		elsif count < 23 then
			t_cs<='0';
			t_rd<='1';
		else
			t_cs<='0';
			t_rd<='0';
			if int='0' then
				t_int<=t_int+1;
			else
				t_int<=0;
			end if;
			if t_int = 2 then
				t_data <= datain;
				count <= 0;
				val <= 0;
			end if;
		end if;
end if;
end process;

if (count < t_data) then
	count <= count + 1;
	val <= val + 129;
end if;

cs<=t_cs;
rd<=t_rd;
--dataout<=t_data;
--dclk <= count;
ld<=t_data;

end aa;