📄 prescale_counter.twr
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Release 9.1i Trace
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
d:\Xilinx91i\bin\nt\trce.exe -ise
D:/ise_book/Example-5-2/Constraints_Demo/prescale_counter_ver/prescale_counter_ver.ise
-intstyle ise -e 3 -s 6 -xml prescale_counter prescale_counter.ncd -o
prescale_counter.twr prescale_counter.pcf -ucf prescale_counter.ucf
Design file: prescale_counter.ncd
Physical constraint file: prescale_counter.pcf
Device,package,speed: xc2v40,cs144,-6 (PRODUCTION 1.121 2006-10-19, STEPPING level 1)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 5 ns HIGH 50%;
63 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 3.027ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_upper_counter = MAXDELAY FROM TIMEGRP "upper_counter" TO TIMEGRP
"upper_counter" TS_clk * 4;
465 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is 3.667ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: OFFSET = OUT 10 ns AFTER COMP "clk";
32 items analyzed, 0 timing errors detected.
Minimum allowable offset is 7.427ns.
--------------------------------------------------------------------------------
All constraints were met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
counter<0> | 6.593(R)|clk_BUFGP | 0.000|
counter<1> | 6.593(R)|clk_BUFGP | 0.000|
counter<2> | 6.584(R)|clk_BUFGP | 0.000|
counter<3> | 6.554(R)|clk_BUFGP | 0.000|
counter<4> | 6.592(R)|clk_BUFGP | 0.000|
counter<5> | 6.592(R)|clk_BUFGP | 0.000|
counter<6> | 7.038(R)|clk_BUFGP | 0.000|
counter<7> | 6.582(R)|clk_BUFGP | 0.000|
counter<8> | 6.828(R)|clk_BUFGP | 0.000|
counter<9> | 6.590(R)|clk_BUFGP | 0.000|
counter<10> | 6.800(R)|clk_BUFGP | 0.000|
counter<11> | 6.829(R)|clk_BUFGP | 0.000|
counter<12> | 7.298(R)|clk_BUFGP | 0.000|
counter<13> | 6.821(R)|clk_BUFGP | 0.000|
counter<14> | 7.056(R)|clk_BUFGP | 0.000|
counter<15> | 7.038(R)|clk_BUFGP | 0.000|
counter<16> | 7.273(R)|clk_BUFGP | 0.000|
counter<17> | 7.082(R)|clk_BUFGP | 0.000|
counter<18> | 6.816(R)|clk_BUFGP | 0.000|
counter<19> | 7.063(R)|clk_BUFGP | 0.000|
counter<20> | 6.838(R)|clk_BUFGP | 0.000|
counter<21> | 6.817(R)|clk_BUFGP | 0.000|
counter<22> | 7.064(R)|clk_BUFGP | 0.000|
counter<23> | 6.591(R)|clk_BUFGP | 0.000|
counter<24> | 6.603(R)|clk_BUFGP | 0.000|
counter<25> | 6.794(R)|clk_BUFGP | 0.000|
counter<26> | 6.832(R)|clk_BUFGP | 0.000|
counter<27> | 7.427(R)|clk_BUFGP | 0.000|
counter<28> | 6.556(R)|clk_BUFGP | 0.000|
counter<29> | 6.820(R)|clk_BUFGP | 0.000|
counter<30> | 6.592(R)|clk_BUFGP | 0.000|
counter<31> | 6.589(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 3.667| | | |
---------------+---------+---------+---------+---------+
OFFSET = OUT 10 ns AFTER COMP "clk";
Largest slack: 3.446 ns; Smallest slack: 2.573 ns; Relative Skew: 0.873 ns;
-----------------------------------------------+-------------+-------------+
PAD | Slack |Relative Skew|
-----------------------------------------------+-------------+-------------+
counter<0> | 3.407| 0.039|
counter<1> | 3.407| 0.039|
counter<2> | 3.416| 0.030|
counter<3> | 3.446| 0.000|
counter<4> | 3.408| 0.038|
counter<5> | 3.408| 0.038|
counter<6> | 2.962| 0.484|
counter<7> | 3.418| 0.028|
counter<8> | 3.172| 0.274|
counter<9> | 3.410| 0.036|
counter<10> | 3.200| 0.246|
counter<11> | 3.171| 0.275|
counter<12> | 2.702| 0.744|
counter<13> | 3.179| 0.267|
counter<14> | 2.944| 0.502|
counter<15> | 2.962| 0.484|
counter<16> | 2.727| 0.719|
counter<17> | 2.918| 0.528|
counter<18> | 3.184| 0.262|
counter<19> | 2.937| 0.509|
counter<20> | 3.162| 0.284|
counter<21> | 3.183| 0.263|
counter<22> | 2.936| 0.510|
counter<23> | 3.409| 0.037|
counter<24> | 3.397| 0.049|
counter<25> | 3.206| 0.240|
counter<26> | 3.168| 0.278|
counter<27> | 2.573| 0.873|
counter<28> | 3.444| 0.002|
counter<29> | 3.180| 0.266|
counter<30> | 3.408| 0.038|
counter<31> | 3.411| 0.035|
-----------------------------------------------+-------------+-------------+
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 560 paths, 0 nets, and 144 connections
Design statistics:
Minimum period: 3.667ns (Maximum frequency: 272.702MHz)
Maximum path delay from/to any node: 3.667ns
Minimum output required time after clock: 7.427ns
Analysis completed Tue Dec 12 16:00:14 2006
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 91 MB
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