jc2_top.twr

Xilinx ISE9.x FPGACPLD设计指南 原书光盘上的源码 包含大量vhdl源码

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Release 9.1i Trace 
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

D:\Xilinx91i\bin\nt\trce.exe -ise
D:/ise_book/Example-6-1/iMPACT_DEMO/jc2_vhd/jc2_vhd.ise -intstyle ise -e 3 -s 5
-xml jc2_top jc2_top.ncd -o jc2_top.twr jc2_top.pcf -ucf jc2_top.ucf

Design file:              jc2_top.ncd
Physical constraint file: jc2_top.pcf
Device,package,speed:     xc3s400,pq208,-5 (PRODUCTION 1.39 2006-10-19)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock CLK
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
LEFT        |    2.305(R)|    0.574(R)|CLK_BUFGP         |   0.000|
RIGHT       |    1.853(R)|    0.420(R)|CLK_BUFGP         |   0.000|
STOP        |    1.764(R)|    0.173(R)|CLK_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock CLK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
Q<0>        |    8.565(R)|CLK_BUFGP         |   0.000|
Q<1>        |    8.031(R)|CLK_BUFGP         |   0.000|
Q<2>        |    8.516(R)|CLK_BUFGP         |   0.000|
Q<3>        |    8.911(R)|CLK_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |    1.760|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Wed Dec 20 14:55:40 2006
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 100 MB