picoblaze_vga.v

Xilinx ISE9.x FPGACPLD设计指南 原书光盘上的源码 包含大量vhdl源码

module picoblaze_vga(
  iRST_N,
  iCLK, // 50MHZ

  iADDR,  // PBus Bus Address
  iDATAIN,// PBus Data in
  iWR,    // PBus Write operation signal
  iRD,    // PBus Read operation signal
  oHC_DBUS,// PBus Data Out  
 
  oHSYNC,
  oVSYNC,
 
  oVGA_RED,
  oVGA_GREEN,
  oVGA_BLUE

);

parameter C_BASEADDR = 8'h00;

input iRST_N;
input iCLK;

input [ 7: 0] iADDR;
input [ 7: 0] iDATAIN;
input         iWR;
input         iRD;

output[ 7: 0] oHC_DBUS;

output oHSYNC;
output oVSYNC;

output [ 2: 0] oVGA_RED;
output [ 2: 0] oVGA_GREEN;
output [ 2: 0] oVGA_BLUE;

wire s_valid;

picoblaze_vga_busif #(.C_BASEADDR(C_BASEADDR))vga_busif(

  .iCLK(iCLK),
  .iRST_N(iRST_N),
  .iADDR(iADDR),
  .iDATAIN(iDATAIN),
  .iWR(iWR),
  .iRD(iRD),
  .oHC_DBUS(oHC_DBUS),
  
  .oVGA_RED(oVGA_RED),
  .oVGA_GREEN(oVGA_GREEN),
  .oVGA_BLUE(oVGA_BLUE),
  .iVALID(s_valid)
);


sync_gen_50M sync_gen_inst(
  .iRST_N(iRST_N),
  .iCLK(iCLK), // 50MHz
  
  .oHSYNC(oHSYNC),
  .oVSYNC(oVSYNC),
  .oVALID(s_valid)
);


endmodule