sync_gen_50m.v

Xilinx ISE9.x FPGACPLD设计指南 原书光盘上的源码 包含大量vhdl源码

module sync_gen_50M(
  iRST_N,
  iCLK, // 50MHz
  
  oHSYNC,
  oVSYNC,
  oVALID
);

input iRST_N;
input iCLK;

output oHSYNC;
output oVSYNC;
output oVALID;


reg sr_hsync;
reg sr_vsync;

reg [10: 0] sr_xcnt;
reg [ 9: 0] sr_ycnt;
reg         sr_valid;


assign oHSYNC = sr_hsync;
assign oVSYNC = sr_vsync;
assign oVALID = sr_valid;



// register sr_xcnt
always @ ( posedge iCLK or negedge iRST_N) begin
  if ( !iRST_N ) begin
    sr_xcnt <= 11'd0;
  end
  else begin
    if ( sr_xcnt == 11'd1039 ) begin
      sr_xcnt <= 11'd0;
    end
    else begin
      sr_xcnt <= sr_xcnt + 1'b1;
    end
  end
end

// register sr_ycnt
always @ ( posedge iCLK or negedge iRST_N) begin
  if ( !iRST_N ) begin
    sr_ycnt <= 10'd0;
  end
  else begin
    if ( sr_ycnt == 10'd665 ) begin
      sr_ycnt <= 10'd0;
    end
    else begin
      if ( sr_xcnt == 11'd1039 ) begin
        sr_ycnt <= sr_ycnt + 1'b1;
      end
      else begin
        sr_ycnt <= sr_ycnt;
      end
    end
  end
end

// register sr_hsync and sr_vsync
always @ ( posedge iCLK or negedge iRST_N ) begin
  if ( !iRST_N ) begin
    sr_hsync <= 1'b0;
    sr_vsync <= 1'b0;
  end
  else begin
    sr_hsync <= ( sr_xcnt < 11'd120 ) ? 1'b1:1'b0;
    sr_vsync <= ( sr_ycnt < 10'd6   ) ? 1'b1:1'b0;
  end
end

// register sr_valid
always @ ( posedge iCLK or negedge iRST_N ) begin
  if ( !iRST_N ) begin
	 sr_valid <= 1'b0;
  end
  else begin
	 sr_valid <= ( ( sr_xcnt > 10'd180 ) && ( sr_xcnt < 10'd980 ) && ( sr_ycnt > 10'd35 ) && ( sr_ycnt < 10'd635 ));
  end
end

endmodule