picoblaze_vga_busif.v

Xilinx ISE9.x FPGACPLD设计指南 原书光盘上的源码 包含大量vhdl源码

module picoblaze_vga_busif(

  iCLK,
  iRST_N,
  iADDR,
  iDATAIN,
  iWR,
  iRD,
  oHC_DBUS,
  
  oVGA_RED,
  oVGA_GREEN,
  oVGA_BLUE,
  iVALID


);

parameter C_BASEADDR = 8'h00;


input         iCLK     ;  // System clock
input         iRST_N   ;  // System RST Low Active
input [ 7: 0] iADDR    ;  // Address Bus 8 bits
input [ 7: 0] iDATAIN  ;  // Data Bus input 8 bits
input         iWR      ;  // Write operation
input         iRD      ;  // Read operation 
output[ 7: 0] oHC_DBUS ;  // Data Bus output 8 bits
input         iVALID   ;

output[ 2: 0] oVGA_RED;  
output[ 2: 0] oVGA_GREEN;
output[ 2: 0] oVGA_BLUE;  



reg [ 2: 0] sr_red;  // offset 0x0     
reg [ 2: 0] sr_green; // offset 0x1
reg [ 2: 0] sr_blue; // offset 0x2

reg [ 7: 0] sr_HC_DBUS       ;

reg         sr_wr;
reg         sr_rd;



wire s_ADDRMATCH_RED;
wire s_ADDRMATCH_GREEN;
wire s_ADDRMATCH_BLUE;


wire s_RD;
wire s_WR;

assign oVGA_RED   = ( iVALID ) ? sr_red   : 3'h0;
assign oVGA_GREEN = ( iVALID ) ? sr_green : 3'h0;
assign oVGA_BLUE  = ( iVALID ) ? sr_blue  : 3'h0;



                                   
assign oHC_DBUS = sr_HC_DBUS;// & { 8{s_RD}};


assign s_ADDRMATCH_RED    = (iADDR == C_BASEADDR       )? 1'b1:1'b0;
assign s_ADDRMATCH_GREEN  = (iADDR == C_BASEADDR + 8'h1)? 1'b1:1'b0;
assign s_ADDRMATCH_BLUE   = (iADDR == C_BASEADDR + 8'h2)? 1'b1:1'b0;


assign s_WR = iWR & (~sr_wr);
assign s_RD = iRD & (~sr_rd);



always @ (
  s_ADDRMATCH_RED   or
  s_ADDRMATCH_GREEN or
  s_ADDRMATCH_BLUE  or
  oHC_DBUS          or
  sr_red            or
  sr_green          or
  sr_blue           or
  iRD               
)begin
  case ({s_ADDRMATCH_RED,s_ADDRMATCH_GREEN,s_ADDRMATCH_BLUE})
    3'b100: begin
      sr_HC_DBUS = {5'h0,sr_red};
    end
    4'b010: begin
      sr_HC_DBUS = {5'h0,sr_green};
    end
    4'b001: begin
      sr_HC_DBUS = {5'h0,sr_blue};
    end
    default: begin
      sr_HC_DBUS = 8'h0;               
    end  
  endcase
end



// register sr_wr
always @ ( posedge iCLK or negedge iRST_N ) begin
  if ( !iRST_N ) begin
    sr_wr <= 1'b0;	
  end
  else begin
    sr_wr <= iWR; 
  end
end

// register sr_rd  
always @ ( posedge iCLK or negedge iRST_N  ) begin
  if ( !iRST_N ) begin
    sr_rd <= 1'b0;	
  end
  else begin
    sr_rd <= iRD;
  end
end

// register sr_red
always @ ( posedge iCLK or negedge iRST_N  ) begin
  if ( !iRST_N ) begin
    sr_red <= 3'h0;	
  end
  else begin
    if ( s_ADDRMATCH_RED & s_WR ) begin
      sr_red <= iDATAIN[ 2: 0];
    end
    else begin
      sr_red <= sr_red;
    end
  end
end

// register sr_green
always @ ( posedge iCLK or negedge iRST_N  ) begin
  if ( !iRST_N ) begin
    sr_green <= 3'h0;	
  end
  else begin
    if ( s_ADDRMATCH_GREEN & s_WR ) begin
      sr_green <= iDATAIN[ 2: 0];
    end
    else begin
      sr_green <= sr_green;
    end
  end
end

// register sr_blue
always @ ( posedge iCLK or negedge iRST_N  ) begin
  if ( !iRST_N ) begin
    sr_blue <= 8'h0;	
  end
  else begin
    if ( s_ADDRMATCH_BLUE & s_WR ) begin
      sr_blue <= iDATAIN[ 2: 0];
    end
    else begin
      sr_blue <= sr_blue;
    end
  end
end
endmodule