system_top.twr

Xilinx ISE9.x FPGACPLD设计指南 原书光盘上的源码 包含大量vhdl源码

--------------------------------------------------------------------------------
Release 8.1i Trace I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

C:\Xilinx\bin\nt\trce.exe -ise pb_emb.ise -intstyle ise -e 3 -l 3 -s 4 -xml
system_top system_top.ncd -o system_top.twr system_top.pcf


Design file:              system_top.ncd
Physical constraint file: system_top.pcf
Device,speed:             xc3s400,-4 (PRODUCTION 1.37 2005-11-04)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock iCLK
--------------+------------+------------+------------------+--------+
              |  Setup to  |  Hold to   |                  |  Clock |
Source        | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
--------------+------------+------------+------------------+--------+
iPUSHBUTTON<0>|    3.412(R)|   -1.300(R)|iCLK_BUFGP        |   0.000|
iPUSHBUTTON<1>|    3.401(R)|   -1.292(R)|iCLK_BUFGP        |   0.000|
iPUSHBUTTON<2>|    2.450(R)|   -0.531(R)|iCLK_BUFGP        |   0.000|
iPUSHBUTTON<3>|    2.883(R)|   -0.838(R)|iCLK_BUFGP        |   0.000|
iRST_N        |    3.273(R)|   -0.803(R)|iCLK_BUFGP        |   0.000|
--------------+------------+------------+------------------+--------+

Clock iCLK to Pad
-------------+------------+------------------+--------+
             | clk (edge) |                  |  Clock |
Destination  | to PAD     |Internal Clock(s) |  Phase |
-------------+------------+------------------+--------+
oHCCP        |   11.358(R)|iCLK_BUFGP        |   0.000|
oHCSI        |   17.713(R)|iCLK_BUFGP        |   0.000|
oHSYNC       |    7.363(R)|iCLK_BUFGP        |   0.000|
oVGA_BLUE<0> |   12.006(R)|iCLK_BUFGP        |   0.000|
oVGA_BLUE<1> |   11.774(R)|iCLK_BUFGP        |   0.000|
oVGA_BLUE<2> |   11.652(R)|iCLK_BUFGP        |   0.000|
oVGA_GREEN<0>|   11.980(R)|iCLK_BUFGP        |   0.000|
oVGA_GREEN<1>|   11.874(R)|iCLK_BUFGP        |   0.000|
oVGA_GREEN<2>|   11.851(R)|iCLK_BUFGP        |   0.000|
oVGA_RED<0>  |   12.225(R)|iCLK_BUFGP        |   0.000|
oVGA_RED<1>  |   12.103(R)|iCLK_BUFGP        |   0.000|
oVGA_RED<2>  |   12.139(R)|iCLK_BUFGP        |   0.000|
oVSYNC       |    7.363(R)|iCLK_BUFGP        |   0.000|
-------------+------------+------------------+--------+

Clock to Setup on destination clock iCLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
iCLK           |   14.961|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Sun Aug 13 10:32:52 2006
--------------------------------------------------------------------------------



Peak Memory Usage: 108 MB