myvga.v

Xilinx ISE9.x FPGACPLD设计指南 原书光盘上的源码 包含大量vhdl源码

// --------------------------------------------------------------------- 
// File     :myVGA.v
// Module   :myVGA,top module
// Function :It is VGA output controller
// At present , the resolution is set to 800*640, refresh rate is set at
// 72HZ. 
// --------------------------------------------------------------------- 
// keywords : 
// ---------------------------------------------------------------------
// Remarks  :
// .System clock is 50MHZ, TFT clock is 50MHZ
// --------------------------------------------------------------------- 
// History: 
// Version  Date       			Author          Description 
// v0.0     2006/08/08    Jiang Zuojie    Original : display 4 vertical color strips 
// V0.1    	2006/08/08		  Jiang Zuojie	   improve resolution to 800*600 refresh rate to     
// --------------------------------------------------------------------- 

//==============================================================================
// DEFINE
//==============================================================================
//width for how many bits for one color
`define    Width_bit_color        3 
//for color data transfer through opb bus
`define    Width_opb_colordata    9
                 
module myVGA ( Sys_clk,
               Sys_rst,
               iBusdata,
               R,
               G,
               B,
               Hsync,
               Vsync
             );
//==============================================================================
// Port Declaration
//==============================================================================
   input                                         Sys_clk;
   input                                         Sys_rst;//at present,use push button to rst
   input       [ 0 : `Width_opb_colordata - 1 ]  iBusdata;//input from opb bus to send color data
   //---------------------------------------------------------------------------
   output      [ 0 : `Width_bit_color - 1 ]      R;//8bit one color output , total is 24bit color
   output      [ 0 : `Width_bit_color - 1 ]      G;
   output      [ 0 : `Width_bit_color - 1 ]      B;
   output                                        Hsync;//horizontal synchronize signal
   output                                        Vsync;//horizontal synchronize signal
//==============================================================================
// Net Declaration
//==============================================================================  
   wire                                          wEnable;//indicate which period of time is valid
//==============================================================================
// ASSIGNMENT
//==============================================================================	

//==============================================================================
//Instantiation
//==============================================================================

// generate horizontal & vertical synchronize signal                     
vga_sync    vga_sync_0 ( .Tft_clk ( Sys_clk ) ,
                         .Sys_rst ( Sys_rst ) ,
                         .Hsync ( Hsync ) ,
                         .Vsync ( Vsync ) ,
                         .Enable ( wEnable )
                       );
// map certain color to output                      
color_map   color_map_0 ( .Sys_clk ( Sys_clk ) ,
                          .Sys_rst ( Sys_rst ) ,
                          .iColordata ( iBusdata ) ,
                          .Enable ( wEnable ) ,
                          .Red ( R ) ,
                          .Green ( G ) ,
                          .Blue ( B )
                        );      
endmodule