opb_ipif.v

Xilinx ISE9.x FPGACPLD设计指南 原书光盘上的源码 包含大量vhdl源码

// --------------------------------------------------------------------- 
// File     :opb_ipif.v
// Module   :opb_ipif
// Function :This module is the interface between opb and userip, it has
// to supply at least 1 addressable reg for software to driver userip,
// the operation must be read and write.
// --------------------------------------------------------------------- 
// keywords : 
// ---------------------------------------------------------------------
// Remarks  :
// --------------------------------------------------------------------- 
// History: 
// Version  Date            Author          Description 
// v0.0     2006/08/16      Jiang Zuojie    Original 
//     
// --------------------------------------------------------------------- 
`define    Width_color_data    9

module opb_ipif ( iCLK         ,
  						iRST       ,
  						iOPB_ABUS    ,
  						iOPB_DBUS    ,
  						iOPB_BE      ,
  						iOPB_RNW     ,
  						iOPB_SELECT  ,
  						iOPB_SEQADDR ,            
  						
  						oHC_errAck   , 
  						oHC_toutSup	 ,
  						oHC_retry    ,  
  						
  						oHC_DBUS     ,
  						oHC_XFERACK	 ,
  						
  						oColor_data
	      				 ); 
	      				 
//==============================================================================
// PARAMETER
//==============================================================================
parameter  C_BASEADDR    =    32'h8000_0000;

//==============================================================================
// Port Declaration: important signals, DBUS, ABUS, RNW, ACK, SELECT
//==============================================================================
input                                                iCLK         ;     // OPB Bus clock               
input                                                iRST       ;     // System RST High Active      
input         [ 31 : 0 ]                             iOPB_ABUS    ;     // Address Bus 32 bits         
input         [ 31 : 0 ]                             iOPB_DBUS    ;     // Data Bus input 32 bits      
input         [  3 : 0 ]                             iOPB_BE      ;     // Byte Enable Singal => Ingore
input                                                iOPB_RNW     ;     // Read and Write Signal       
input                                                iOPB_SELECT  ;     // Module Select Signal        
input                                                iOPB_SEQADDR ;                                  
output        [ 31 : 0 ]                             oHC_DBUS     ;     // slave data bus which used to serve for master on OPB      
output                                               oHC_XFERACK  ;     // Bus Acknowledge Signal      
                                                                                                     
output                                               oHC_errAck   ;     // Don't Use. Connect to GND   
output                                               oHC_toutSup  ;     // Don't Use. Connect to GND   
output                                               oHC_retry    ;     // Don't Use. Connect to GND   
                                                                                                                                                                                                                     
output        [ `Width_color_data - 1 : 0 ]          oColor_data  ;     //output to colormap                             
   
//==============================================================================
// Net Declaration
//============================================================================== 
reg 		        [ `Width_color_data - 1 : 0 ]          sr_data      ;     //internal reg to receive data from opb
reg                                                  sr_ack       ;     //indicate when to ack request from master
reg                                                  sr_ms        ;     //one of 2 forces to activate sr_ack, represent addr match 
reg                                                  sr_ms_ff     ;     //the other reg to activate sr_ack, actually, it was 1 clk time delay than sr_ms, that is to catch rising edge of addr_match
wire                                                 s_ADDRMATCH  ;     //indicata whether requested addr is valid
wire                                                 s_WR         ;     //indicate write operation
wire                                                 s_RD         ;     //indicate read operation

//==============================================================================
// ASSIGNMENT
//==============================================================================
	
//---------------------------------------------------------------------------
// assign some fixed value to bus signals
//---------------------------------------------------------------------------
assign     oHC_errAck    =    1'b0;   // Don't Use. Connect to GND     
assign     oHC_toutSup   =    1'b0;   // Don't Use. Connect to GND 
assign     oHC_retry     =    1'b0;   // Don't Use. Connect to GND 

assign     oColor_data [ `Width_color_data - 1 : 0 ] = sr_data [ `Width_color_data - 1 : 0 ];

assign     s_ADDRMATCH = ( iOPB_SELECT && iOPB_ABUS == C_BASEADDR ) ? 1'b1:1'b0;//chip select and opb_addr has to valid on the same time

assign     s_WR = ( s_ADDRMATCH && !iOPB_RNW ) ? 1'b1: 1'b0;//addr match and RNW low means to write
assign     s_RD = ( s_ADDRMATCH &&  iOPB_RNW ) ? 1'b1: 1'b0;

assign     oHC_DBUS = ( s_RD ) ? { 23'h0, sr_data } : 32'h0;
//assign     oHC_DBUS = ( s_RD ) ? { ( 32 - `Width_color_data )'h0, sr_data [ `Width_color_data - 1 : 0 ] } : 32'h0;//read color infor to opb bus
assign     oHC_XFERACK = sr_ack ;

//==============================================================================
// Implement: NOTE, THE EXTERN RST IS ACTIVE LOW
//==============================================================================									
   
//---------------------------------------------------------------------------
// 1 reg: sr_ack, ack to request from master, drive by another regs
//---------------------------------------------------------------------------
always @ ( posedge iCLK or posedge iRST ) begin
  if ( iRST ) begin
     sr_ack <= 1'b0;	
  end
  else begin
     sr_ack <= sr_ms & ~sr_ms_ff; 
  end
end

// register sr_ms  
always @ ( posedge iCLK or posedge iRST  ) begin
  if ( iRST ) begin
    sr_ms <= 1'b0;	
  end
  else begin
    sr_ms <= s_ADDRMATCH;
  end
end

// register sr_ms_ff
always @ ( posedge iCLK or posedge iRST  ) begin
  if ( iRST ) begin
    sr_ms_ff <= 1'b0;	
  end
  else begin
    sr_ms_ff <= sr_ms;
  end
end

//---------------------------------------------------------------------------
// 1 reg: sr_data, receive input data from bus or output data to bus
//---------------------------------------------------------------------------
always @ ( posedge iCLK or posedge iRST  ) begin
  if ( iRST ) begin
    sr_data <= `Width_color_data'b111_000_000;	
  end
  else begin
    if ( s_WR && sr_ms & ~sr_ms_ff ) begin
      sr_data <= iOPB_DBUS [ `Width_color_data -1 : 0 ];	
    end
    else begin
      sr_data <= sr_data;	
    end
  end
end

endmodule