opb_hc164_busif.v

Xilinx ISE9.x FPGACPLD设计指南 原书光盘上的源码 包含大量vhdl源码

module opb_hc164_busif(

  iCLK,
  iRST_N,
  iOPB_ABUS,
  iOPB_DBUS,
  iOPB_BE,
  iOPB_RNW,
  iOPB_SELECT,
  iOPB_SEQADDR,            
  
  oHC_errAck, 
  oHC_toutSup,
  oHC_retry,  
  
  oHC_DBUS,
  oHC_XFERACK,

  oLED_VAL,
  oSEG_VAL,
  oSEG_DOT


);

parameter C_BASEADDR = 32'h8000_0000;


input         iCLK     ;  // OPB Bus clock
input         iRST_N   ;  // System RST High Active
input [31: 0] iOPB_ABUS;  // Address Bus 32 bits
input [31: 0] iOPB_DBUS;  // Data Bus input 32 bits
input [ 3: 0] iOPB_BE  ;  // Byte Enable Singal => Ingore
input         iOPB_RNW ;  // Read and Write Signal
input         iOPB_SELECT;// Module Select Signal 
input         iOPB_SEQADDR;  
output[31: 0] oHC_DBUS   ;// Data Bus output 32bits
output        oHC_XFERACK;// Bus Acknowledge Signal

output        oHC_errAck ;// Don't Use. Connect to GND  
output        oHC_toutSup;// Don't Use. Connect to GND 
output        oHC_retry  ;// Don't Use. Connect to GND   



output[ 3: 0] oLED_VAL;
output[15: 0] oSEG_VAL;
output[ 3: 0] oSEG_DOT;

reg [23: 0] sr_data; // sr_data : [23:20] => oLED_VAL [19: 4] => oSEG_VAL [ 3: 0] => oSEG_DOT
reg         sr_ack;
reg         sr_ms;
reg         sr_ms_ff;

wire s_ADDRMATCH;
wire s_WR;
wire s_RD;


assign oLED_VAL [ 3 : 0 ] = sr_data [ 23 : 20 ];
assign oSEG_VAL [15 : 0 ] = sr_data [ 19 :  4 ];
assign oSEG_DOT [ 3 : 0 ] = sr_data [  3 :  0 ];

assign oHC_errAck  = 1'b0; 
assign oHC_toutSup = 1'b0;
assign oHC_retry   = 1'b0; 

assign s_ADDRMATCH = (iOPB_SELECT && iOPB_ABUS == C_BASEADDR )? 1'b1:1'b0;

assign s_WR = (s_ADDRMATCH && !iOPB_RNW ) ? 1'b1: 1'b0;
assign s_RD = (s_ADDRMATCH &&  iOPB_RNW ) ? 1'b1: 1'b0;

assign oHC_DBUS = ( s_RD ) ? { 8'h0, sr_data } : 32'h0;
assign oHC_XFERACK = sr_ack ;


// register sr_ack
always @ ( posedge iCLK or negedge iRST_N ) begin
  if ( !iRST_N ) begin
    sr_ack <= 1'b0;	
  end
  else begin
    sr_ack <= sr_ms & ~sr_ms_ff; 
  end
end

// register sr_ms  
always @ ( posedge iCLK or negedge iRST_N  ) begin
  if ( !iRST_N ) begin
    sr_ms <= 1'b0;	
  end
  else begin
    sr_ms <= s_ADDRMATCH;
  end
end

// register sr_ms_ff
always @ ( posedge iCLK or negedge iRST_N  ) begin
  if ( !iRST_N ) begin
    sr_ms_ff <= 1'b0;	
  end
  else begin
    sr_ms_ff <= sr_ms;
  end
end
always @ ( posedge iCLK or negedge iRST_N  ) begin
  if ( !iRST_N ) begin
    sr_data <= 24'hA12343;	
  end
  else begin
    if ( s_WR && sr_ms & ~sr_ms_ff ) begin
      sr_data <= iOPB_DBUS[23: 0];	
    end
    else begin
      sr_data <= sr_data;	
    end
  end
end

endmodule