c_8259.vhd.txt

Vhdl硬件描述语言例子集

signal ISR_A : STD_LOGIC_VECTOR (7 downto 0);
signal ISR_CLR : STD_LOGIC_VECTOR (7 downto 0);
signal ISR_O : STD_LOGIC_VECTOR (7 downto 0);
signal BUS386 : STD_LOGIC_VECTOR (7 downto 0);

begin

----  Component instantiations  ----

U0 : pr_cell8
  port map(
       D_OUT => R_OUT,
       FREEZE => FREEZE,
       IMR => IMR,
       IR => IR,
       IRR_N => IRR_O,
       IRR_WT => IRR_WP,
       ISR_ACCEPT => ISR_ACCEPT,
       ISR_CLR => ISR_CLR,
       ISR_O => ISR_O,
       LEVEL => LEVEL,
       MASK => MASK,
       READ => READ,
       RESET => RESET
 );

U1 : ipr_res
 port map(
       EOI_1 => EOI_1,
       EOI_2 => EOI_2,
       EOI_3 => EOI_3,
       EOI_4 => EOI_4,
       EOI_5 => EOI_5,
       EOI_N => EOI_N,
       IPR => IPR,
       ISR_A => ISR_A,
       ISR_CLR => ISR_CLR,
       N_WR => N_WR,
       RESET => RESET
 );

U2 : brlshft8_r
  port map(
       I => ISR_O,
       O => ISR_A,
       S => IPR
  );

U3 : brlshft8_r
  port map(
       I => IRR_O,
       O => IRR_A,
       S => IPR
 );

U4 : irr_w
  port map(
       IRR_M => IRR_A,
       IRR_W => BUS386,
       IR_WORK => IR_WORK_A,
       ISR_ACCEPT => FREEZE,
       ISR_M => ISR_A,
       RESET => RESET
  );

U5 : isr_set
  port map(
       IPR => IPR,
       IRR_W => BUS386,
       IRR_WP_OUT => IRR_WP,
       IR_NR_WORK => IR_NR
 );

---- Terminal assignment ----

    -- Output buffer terminals
    IR_NR_WORK <= IR_NR;
    IR_WORK <= IR_WORK_A;

end Controll;


------------------------------------------------------------------------------------
-- C-8259 -----------------------------------------------------------------------
------------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {C_8259} architecture {C_8259_arch}}

library IEEE;
use IEEE.std_logic_1164.all;

entity C_8259 is
	port(
		A0 : in std_logic;
		INT : out std_logic;
		nCS : in std_logic;
		nINTA : in std_logic;
		nRD : in std_logic;
		nWR : in std_logic;
		nSP : in std_logic;
		D : inout std_logic_vector (7 downto 0);
		CAS : inout std_logic_vector (2 downto 0);
		IR : in std_logic_vector(7 downto 0)
	);
end C_8259;

--}} End of automatically maintained section

architecture C_8259_arch of C_8259 is

	component FDCE
	port(
		Q : out std_logic;
		D : in std_logic;
		C : in std_logic;
		CE : in std_logic;
		CLR : in std_logic);
	end component;

	component FDCEx8
	port(
		I : in std_logic_vector(7 downto 0);
		O : out std_logic_vector(7 downto 0);
		C : in std_logic;
		CE : in std_logic;
		CLR : in std_logic);
	end component;

	component Controll
	port(
		ISR_ACCEPT : in std_logic;
		EOI_1 : in std_logic;
		EOI_2 : in std_logic;
		EOI_3 : in std_logic;
		EOI_4 : in std_logic;
		EOI_5 : in std_logic;
		FREEZE : in std_logic;
		LEVEL : in std_logic;
		MASK : in std_logic;
		N_WR : in std_logic;
		READ : in std_logic;
		RESET : in std_logic;
		EOI_N : in std_logic_vector(2 downto 0);
		IMR : in std_logic_vector(7 downto 0);
		IR : in std_logic_vector(7 downto 0);
		IR_WORK : out std_logic;
		IR_NR_WORK : out std_logic_vector(2 downto 0);
		R_OUT : out std_logic_vector(7 downto 0));
	end component;

	signal SNGL: STD_LOGIC; -- 1: Single, 0: Cascade

	-- registers for programming words
	signal P: std_logic_vector (3 downto 1); -- ICW steps
	signal I: std_logic_vector (3 downto 1); -- interrupt steps
	signal T: std_logic_vector (8 downto 1);
	signal CLR_I1, CLR_I2, CLR_I3, CLR_P1, CLR_P2, CLR_P3 : std_logic;

	-- ENABLE signals
	signal EN, EN_DATA_SLAVE, EN_I1, EN_I2, EN_I3,
		  EN_CAS_OUT, EN_CAS_IN : std_logic;

	-- not nWR and not nRD;
	signal WR, RD: std_logic;

	-- interval signal
	signal INTERVAL: std_logic;

	-- address of interrupts (MSB)
	signal A_MSB: std_logic_vector (15 downto 5);

	-- MASTER and SLAVE signals
	signal MASTER, SLAVE, SLAVE_E: std_logic;

	-- constant for the first interrupt vector byte
	constant CALL: STD_LOGIC_VECTOR (7 downto 0) := "11001101"; -- (0CDH) 	

	-- signals used to end INT output
	signal CLR_INT, CLR_INT_A, EN_CLR_INT_A_0 : std_logic;

	-- nINTA signal
	signal INTA: std_logic;

	--help signals used to activate cascade outputs
	signal SM0, SM1, SM2, SM3, SM4, SM5, SM6, SM7: std_logic;

	-- help signals to set cascade inout ports
	signal CAS0_IN : std_logic;
	signal CAS1_IN : std_logic;
	signal CAS2_IN : std_logic;

	-- MASK registers
	signal SET_MASK: std_logic;

	-- Poll command WORD
	signal P_WORD: std_logic_vector (7 downto 0);

	-- ICW3 values
	signal MS_N: std_logic_vector (7 downto 0);

	-- POLLED MODE
	signal POLLED_MODE: std_logic;
	signal EN_POLLED_0: std_logic;
	signal CLR_READ_A, CLR_P_MODE, CLR_CLR_READ_A: std_logic;

	-- READ word
	signal READ_WORD: std_logic_vector (7 downto 0);

	-- Read flags
	signal SET_READ_ISR_nIRR, READ_ISR_nIRR: std_logic;

	-- Enable signal to write registers C-8259ed by first programming word
	signal EnWR_P1: std_logic;

	-- Interrupt request flag
	signal IR_WORK: std_logic;
	-- Number of actually requesting interrupt
	signal IR_NR_WORK: std_logic_vector (2 downto 0);

	-- when '1' than is enabled level triggered mode
	-- when '0' then is enabled edge triggered mode
	signal LEVEL: std_logic;

	-- end of interrupt flags
	signal EOI_1, EOI_2, EOI_3, EOI_4, EOI_5 : std_logic;

	-- A flag for special mask mode
	signal MASK: std_logic;

	-- It freezes requested interrupts during nINTA and POLLED MODE 
	--  sequence only
	signal FREEZE: std_logic;

	-- GND and VCC signals
	signal GND,VCC: std_logic;

	-- Enable signal to write registers C-8259ed by first programming word
	signal EnWR_P3: std_logic;

	-- inverted INT signal
	signal N_INT, INT_V: std_logic;

	-- ISR_ACCEPT - activated when read part of polled mode;
	signal ISR_ACCEPT: std_logic;

	-- There are not slaves at IR inputs of MASTER
	signal NO_SLAVE: std_logic;

	-- Interrupt mask register
	signal IMR: std_logic_vector(7 downto 0);

	-- signals to use during requesting interrupt with higher pririty
	signal CLR_OLD_IR, CLR_CLR_OLD_IR, IR_WORK_S: std_logic;

signal nINTAn: std_logic;
signal nRDn: std_logic;
signal nWRn: std_logic;
begin

---------------------------------------------------------------------------------------
	-- conditions for transitions

	-- 1. Initialization words
	T(1) <= (not A0) and (not nRD) and EN; -- now ICW1 (nWR='0')
	T(2) <= P(1) and A0 and (not nRD) and EN; -- now ICW2 (nWR='0')
	T(3) <= P(2) and A0 and (not nRD) and EN; -- now ICW3 (nWR='0')
	-- 2. OCW words
	T(4) <= A0 and (not nRD) and (not P(1)) and EN 
			and (not (P(2) and (not SNGL)) ) and WR; -- now OCW1 (nWR='1')
	T(5) <= (not A0) and (D(3) nor D(4)) and (not nRD) and EN; -- now OCW2
	T(6) <= (not A0) and D(3) and (not D(4)) and (not nRD) and EN; -- now OCW3
	T(7) <= (not A0) and (not nWR) and EN and RD; -- read part of OCW3

	-- 5. IMR read
	T(8) <= A0 and (not nWR) and EN and (not P(1)) and (not P(2)) and RD; -- (nRD='0')

	-- places
	-- 1. Initialization words
	CLR_P1 <= (not T(1)) and P(2);
	nWRn <= not nWR;
	SET_P1: FDCE port map (P(1), D(4), nWRn, T(1), CLR_P1);
	EnWR_P1 <= T(1) and D(4);

	CLR_P2 <= (not T(2)) and P(3);
	SET_P2: FDCE port map (P(2), T(2), nWRn,VCC, CLR_P2);

	CLR_P3 <= (not T(3)) and P(1);
	SET_P3: FDCE port map (P(3), T(3), nWRn,VCC, CLR_P3);
	EnWR_P3 <= T(3) and (not SNGL);

---------------------------------------------------------------------------------------

	--- OCW1
	SET_IMR: FDCEx8 port map (D, IMR, nWRn, T(4), P(1));

---------------------------------------------------------------------------------------
	-- SIGNALS assigment

	-- 1. Registers initiate by programming words

	-- set SNGL
	SET_SNGL: FDCE port map (SNGL, D(1), nWRn, EnWR_P1, GND);

	-- set Interval
	SET_INTERVAL: FDCE port map (INTERVAL, D(2), nWRn, EnWR_P1, GND);

	-- set LEVEL
	SET_LEVEL: FDCE port map (LEVEL, D(3), nWRn, EnWR_P1, GND);

	-- A_MSB
	SET_A_MSB8_15: FDCEx8 port map (D, A_MSB(15 downto 8), nWRn, T(2), GND);

	-- the middle part of address
	SET_A_MSB6: FDCE port map (A_MSB(6), D(6), nWRn, EnWR_P1, GND);
	SET_A_MSB7: FDCE port map (A_MSB(7), D(7), nWRn, EnWR_P1, GND);
	SET_A_MSB5: FDCE port map (A_MSB(5), D(5), nWRn, EnWR_P1, GND);

	-- number of a SLAVE or MASTER module when ICW3
	SET_MS_N: FDCEx8 port map (D, MS_N, nWRn, EnWR_P3, P(1));

---------------------------------------------------------------------------------------
	-- registers initiate by OCW2
	-- end of interrupts when OCW2:
	EOI_1 <= (not D(7)) and (not D(6)) and D(5) and T(5);
	EOI_2 <= (not D(7)) and D(6) and D(5) and T(5);
	EOI_3 <= D(7) and (not D(6)) and D(5) and T(5);
	EOI_4 <= D(7) and D(6) and D(5) and T(5);
	EOI_5 <= D(7) and D(6) and (not D(5)) and T(5);

-----------------------------------------------------------------------------------------
	-- registers initiate by OCW3

	-- special mask
	SET_MASK <= D(6) and T(6);
	SET_MASK_FD: FDCE port map (MASK, D(5), nWRn, SET_MASK, P(1));

	-- READ ISR and IRR
	SET_READ_ISR_nIRR <= (not D(2)) and D(1) and T(6);
	SET_READ_ISR_FD: FDCE port map 
		(READ_ISR_nIRR, D(0), nWRn, SET_READ_ISR_nIRR, P(1));

	-- POLLED COMMAND
	EN_POLLED_0 <= D(2) and T(6);
	SET_P_MODE: FDCE port map (POLLED_MODE, D(2), nWRn, T(6), CLR_P_MODE);
	CLR_P_MODE <= CLR_READ_A or P(1);

	-- CLR_Polled_mode
	CLR_CLR_READ_A <= P(1) or (not POLLED_MODE);
	nRDn <= not nRD;
	SET_CLEAR_POLLED: FDCE port map 
		(CLR_READ_A, POLLED_MODE, nRDn, T(7), CLR_CLR_READ_A);

---------------------------------------------------------------------------------------
	-- registers and signals initiate by interrupts

	-- 1. IR works
	CLR_I1 <= I(2) or P(1) or CLR_OLD_IR;
	SET_I1: FDCE port map (I(1), INT_V, INTA,VCC, CLR_I1);
	CLR_I2 <= I(3) or P(1) or CLR_OLD_IR;
	SET_I2: FDCE port map (I(2),VCC, INTA, I(1), CLR_I2);
	CLR_I3 <= ((not nINTA) and I(3)) or P(1);
	SET_I3: FDCE port map (I(3), I(2), INTA,VCC, CLR_I3);

	-- 2. IR works			   
	-- Here comming an interrupt with higher priority
	CLR_CLR_OLD_IR <= N_INT or P(1);
	SET_CLR_OLD_IR: FDCE port map 
		(CLR_OLD_IR, INT_V, IR_WORK,VCC, CLR_CLR_OLD_IR);

	-- INT sets
	EN_CLR_INT_A_0 <= I(3) and (not (SLAVE_E and (not EN_DATA_SLAVE)));
	nINTAn <= not nINTA;
	SET_CLR_INTA: FDCE port map (CLR_INT_A,VCC, nINTAn, EN_CLR_INT_A_0, N_INT);
	CLR_INT <= CLR_INT_A or P(1) or CLR_READ_A or (CLR_OLD_IR and nINTA);

	IR_WORK_S <= (not I(1)) and (not nINTA) and (not CLR_OLD_IR);
	process (CLR_INT, IR_WORK_S, IR_WORK, FREEZE)
	begin
		if CLR_INT='1' then
			INT_V <= '0';
		elsif FREEZE='0' then
			if IR_WORK_S='1' then
				INT_V <= IR_WORK;
			end if;
		end if;
	end process;

	N_INT <= not INT_V;
	P_WORD(7) <= INT_V;

	SET_P_WORD0: FDCE port map (P_WORD(0), IR_NR_WORK(0), ISR_ACCEPT,VCC, P(1));
	SET_P_WORD1: FDCE port map (P_WORD(1), IR_NR_WORK(1), ISR_ACCEPT,VCC, P(1));
	SET_P_WORD2: FDCE port map (P_WORD(2), IR_NR_WORK(2), ISR_ACCEPT,VCC, P(1));

	INT <= INT_V;

	-- ISR_ACCEPT
	ISR_ACCEPT <= (POLLED_MODE and RD) or 
		(I(1) and nINTA and IR_WORK and (not (SLAVE_E and (not EN_DATA_SLAVE))));

	-- FREEZE
	FREEZE <= INTA or POLLED_MODE;

	-- DATA_OUT when SLAVE
	EN_DATA_SLAVE <= SLAVE and (not SNGL) and 
						(not (CAS0_IN xor MS_N(0))) and
						(not (CAS1_IN xor MS_N(1))) and 
						(not (CAS2_IN xor MS_N(2)));

	-- Enable signals for DATA_OUT
	EN_I1 <= I(1) and INTA and (SNGL or MASTER);
	EN_I2 <= I(2) and INTA and (SNGL or EN_DATA_SLAVE or (MASTER and NO_SLAVE));
	EN_I3 <= I(3) and INTA and (SNGL or EN_DATA_SLAVE or (MASTER and NO_SLAVE));

---------------------------------------------------------------------------------------
	-- DATA_OUT

	D(7 downto 6) <= CALL(7 downto 6) when (EN_I1='1') else
			A_MSB(7 downto 6) when (EN_I2='1') else
			A_MSB(15 downto 14) when (EN_I3='1') else 
			IMR(7 downto 6) when (T(8)='1') else
			READ_WORD(7 downto 6) when ( (T(7) and (not POLLED_MODE)) ='1' ) else
			P_WORD(7 downto 6) when ( (POLLED_MODE and T(7)) = '1' ) else
			"ZZ";

	D(5) <= CALL(5) when (EN_I1='1') else
			A_MSB(5) when ( (EN_I2 and INTERVAL) ='1') else
			P_WORD(2) when ( (EN_I2 and (not INTERVAL)) ='1') else
			A_MSB(13) when (EN_I3='1') else 
			IMR(5) when (T(8)='1') else
			READ_WORD(5) when ( (T(7) and (not POLLED_MODE)) ='1' ) else
			P_WORD(5) when ( (POLLED_MODE and T(7)) = '1' ) else
			'Z';

	D(4) <= CALL(4) when (EN_I1='1') else
			P_WORD(2) when ( (EN_I2 and INTERVAL) ='1') else
			P_WORD(1) when ( (EN_I2 and (not INTERVAL)) ='1') else
			A_MSB(12) when (EN_I3='1') else 
			IMR(4) when (T(8)='1') else
			READ_WORD(4) when ( (T(7) and (not POLLED_MODE)) ='1' ) else
			P_WORD(4) when ( (POLLED_MODE and T(7)) = '1' ) else
			'Z';

	D(3) <= CALL(3) when (EN_I1='1') else
			P_WORD(1) when ( (EN_I2 and INTERVAL) ='1') else
			P_WORD(0) when ( (EN_I2 and (not INTERVAL)) ='1') else
			A_MSB(11) when (EN_I3='1') else 
			IMR(3) when (T(8)='1') else
			READ_WORD(3) when ( (T(7) and (not POLLED_MODE)) ='1' ) else
			P_WORD(3) when ( (POLLED_MODE and T(7)) = '1' ) else
			'Z';

	D(2) <= CALL(2) when (EN_I1='1') else
			P_WORD(0) when ( (EN_I2 and INTERVAL) ='1') else
			'0' when ( (EN_I2 and (not INTERVAL)) ='1') else
			A_MSB(10) when (EN_I3='1') else 
			IMR(2) when (T(8)='1') else
			READ_WORD(2) when ( (T(7) and (not POLLED_MODE)) ='1' ) else
			P_WORD(2) when ( (POLLED_MODE and T(7)) = '1' ) else
			'Z';

	D(1 downto 0) <= CALL(1 downto 0) when (EN_I1='1') else
			"00" when (EN_I2='1') else
			A_MSB(9 downto 8) when (EN_I3='1') else 
			IMR(1 downto 0) when (T(8)='1') else
			READ_WORD(1 downto 0) when ( (T(7) and (not POLLED_MODE)) ='1' ) else
			P_WORD(1 downto 0) when ( (POLLED_MODE and T(7)) = '1' ) else
			"ZZ";

---------------------------------------------------------------------------------------
	-- There are not slaves at IR inputs of MASTER
	NO_SLAVE <= not (SM7 or SM6 or SM5 or SM4 or SM3 or SM2 or SM1 or SM0);

	-- There are activate cascade signals when MASTER
	-- CAScade help outputs
	SM7 <= MS_N(7) and P_WORD(2) and P_WORD(1) and P_WORD(0);
	SM6 <= MS_N(6) and P_WORD(2) and P_WORD(1) and (not P_WORD(0));
	SM5 <= MS_N(5) and P_WORD(2) and (not P_WORD(1)) and P_WORD(0);
	SM4 <= MS_N(4) and P_WORD(2) and (not P_WORD(1)) and (not P_WORD(0));
	SM3 <= MS_N(3) and (not P_WORD(2)) and P_WORD(1) and P_WORD(0);
	SM2 <= MS_N(2) and (not P_WORD(2)) and P_WORD(1) and (not P_WORD(0));
	SM1 <= MS_N(1) and (not P_WORD(2)) and (not P_WORD(1)) and P_WORD(0);
	SM0 <= MS_N(0) and (not P_WORD(2)) and (not P_WORD(1)) and (not P_WORD(0));

	-- cascade output when MASTER
	EN_CAS_OUT <= MASTER and (not SNGL) and (I(1) or I(2) or I(3));
	CAS(2) <= '1' when ( ((SM4 or SM5 or SM6 or SM7) and EN_CAS_OUT)='1' ) else
			'0' when ((MASTER = '1') and (SNGL = '0')) else
			'Z';
	CAS(1) <= '1' when ( ((SM2 or SM3 or SM6 or SM7) and EN_CAS_OUT)='1' ) else
			'0' when ((MASTER = '1') and (SNGL = '0')) else
			'Z';
	CAS(0) <= '1' when ( ((SM1 or SM3 or SM5 or SM7) and EN_CAS_OUT)='1' ) else
			'0' when ((MASTER = '1') and (SNGL = '0')) else
			'Z';

	EN_CAS_IN <= (I(1) or I(2) or I(3)) and SLAVE and (not SNGL);
	CAS0_IN <= CAS(0) and EN_CAS_IN;
	CAS1_IN <= CAS(1) and EN_CAS_IN;
	CAS2_IN <= CAS(2) and EN_CAS_IN;

---------------------------------------------------------------------------------------
	MASTER <= nSP;
	SLAVE <= not nSP;
	SLAVE_E <= (not SNGL) and (not nSP);
	EN <= nCS;
	WR <= nWR;
	RD <= nRD;
	INTA <= nINTA;
	P_WORD(6 downto 3) <= "0000";
	GND <= '0';
	VCC <= '1';

---------------------------------------------------------------------------------------
	-- CONTROLLER component - signals connections

	SET_CONTROLLER:
	CONTROLL port map (	 
		ISR_ACCEPT => ISR_ACCEPT,
		R_OUT => READ_WORD,
		IMR => IMR,
		IR_WORK => IR_WORK,
		MASK => MASK,
		IR_NR_WORK => IR_NR_WORK,
		IR => IR,
		LEVEL => LEVEL,
		RESET => P(1),
		EOI_1 => EOI_1,
		EOI_2 => EOI_2,
		EOI_3 => EOI_3,
		EOI_4 => EOI_4,
		EOI_5 => EOI_5,
		EOI_N => D (2 downto 0),
		FREEZE => FREEZE,
		READ => READ_ISR_nIRR,
		N_WR => nWRn
	);

end C_8259_arch;