c_8259.vhd.txt

Vhdl硬件描述语言例子集

       O => MO0,
       S0 => S(1)
  );

U16 : M2_1
  port map(
       D0 => MO0,
       D1 => MO4,
       O => O(0),
       S0 => S(2)
  );

U17 : M2_1
  port map(
       D0 => MO1,
       D1 => MO5,
       O => O(1),
       S0 => S(2)
  );

U18 : M2_1
  port map(
       D0 => MO2,
       D1 => MO6,
       O => O(2),
       S0 => S(2)
  );

U19 : M2_1
  port map(
       D0 => MO3,
       D1 => MO7,
       O => O(3),
       S0 => S(2)
  );

U20 : M2_1
  port map(
       D0 => MO4,
       D1 => MO0,
       O => O(4),
       S0 => S(2)
  );

U21 : M2_1
  port map(
       D0 => MO5,
       D1 => MO1,
       O => O(5),
       S0 => S(2)
  );

U22 : M2_1
  port map(
       D0 => MO6,
       D1 => MO2,
       O => O(6),
       S0 => S(2)
  );

U23 : M2_1
  port map(
       D0 => MO7,
       D1 => MO3,
       O => O(7),
       S0 => S(2)
  );

end BRLSHFT8_L;


------------------------------------------------------------------------------------
-- transparent latch when GATE='0' ----------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity D_LATCH is
	 port(
		 FREEZE : in STD_LOGIC;
		 IRR_EN1 : in STD_LOGIC;
		 RESET : in STD_LOGIC;
		 IRR : out STD_LOGIC
	     );
end D_LATCH;

architecture D_LATCH of D_LATCH is
begin
   MAIN: process (FREEZE, RESET, IRR_EN1)
   begin
	   	if RESET='1' then
			IRR <= '0';
		elsif FREEZE='0' then
			IRR <= IRR_EN1;
		end if;
	end process;
end D_LATCH;

------------------------------------------------------------------------------------
-- eight transparent latches ----------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity D_LATCH8 is
	 port(
		 GATE : in STD_LOGIC;
		 I : in STD_LOGIC_VECTOR(7 downto 0);
		 RESET : in STD_LOGIC;
		 O : out STD_LOGIC_VECTOR(7 downto 0)
	     );
end D_LATCH8;

architecture D_LATCH8 of D_LATCH8 is
	component D_LATCH
	port(
		FREEZE : in std_logic;
		IRR_EN1 : in std_logic;
		RESET : in std_logic;
		IRR : out std_logic);
	end component;

begin

	D_LATCH_8: for M in 7 downto 0 generate
		D_LATCH_M: D_LATCH port map(
			FREEZE => GATE,
			IRR_EN1 => I(M),
			RESET => RESET,
			IRR => O(M)
		);
	end generate;

end D_LATCH8;


------------------------------------------------------------------------------------
-- GATES ------------------------------------------------------------------------
------------------------------------------------------------------------------------


------------------------------------------------------------------------------------
-- Inverter ---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity INV is
	port (
        I0: in STD_LOGIC;
        O: out STD_LOGIC
    );
end INV;

architecture INV of INV is
begin
	O <= not I0;
end INV;

------------------------------------------------------------------------------------
-- AND2 -------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity AND2 is
    port (
        I0: in STD_LOGIC;
        I1: in STD_LOGIC;
        O: out STD_LOGIC
    );
end AND2;

architecture AND2 of AND2 is
begin
	O <= I0 and I1;
end AND2;

------------------------------------------------------------------------------------
-- AND2B1 -----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity and2b1 is
    port (
        I0: in STD_LOGIC;
        I1: in STD_LOGIC;
        O: out STD_LOGIC
    );
end and2b1;

architecture and2b1 of and2b1 is
begin
  O <= I0 and (not I1);
end and2b1;

------------------------------------------------------------------------------------
-- AND3B1 -----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity AND3B1 is
    port (
        I0: in STD_LOGIC;
        I1: in STD_LOGIC;
        I2: in STD_LOGIC;
        O: out STD_LOGIC
    );
end AND3B1;

architecture AND3B1 of AND3B1 is
begin
	O <= (not I0) and I1 and I2;
end AND3B1;

------------------------------------------------------------------------------------
-- OR2 --------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity or2 is
    port (
        I1: in STD_LOGIC;
        I2: in STD_LOGIC;
        O: out STD_LOGIC
    );
end or2;

architecture or2 of or2 is
begin
  O <= I1 or I2;
end or2;

------------------------------------------------------------------------------------
-- OR3 --------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity or3 is
    port (
        I0: in STD_LOGIC;
        I1: in STD_LOGIC;
        I2: in STD_LOGIC;
        O: out STD_LOGIC
    );
end or3;

architecture or3 of or3 is
begin
  O <= I0 or I1 or I2;
end or3;

------------------------------------------------------------------------------------
-- OR4 --------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity or4 is
    port (
        I1: in STD_LOGIC;
        I2: in STD_LOGIC;
        I3: in STD_LOGIC;
        I4: in STD_LOGIC;
        O: out STD_LOGIC
    );
end or4;

architecture or4 of or4 is
begin
  O <= I1 or I2 or I3 or I4;
end or4;

------------------------------------------------------------------------------------
-- OR8 --------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity or8 is
    port (
        I: in STD_LOGIC_VECTOR (7 downto 0);
        O: out STD_LOGIC
    );
end or8;

architecture or8_arch of or8 is
begin
	O <= I(0) or I(1) or I(2) or I(3) or I(4) or I(5) or I(6) or I(7);
end or8_arch;


------------------------------------------------------------------------------------
-- PRIOR_CELL -------------------------------------------------------------------
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity Prior_cell is
  port(
       FREEZE : in STD_LOGIC;
       IMR : in STD_LOGIC;
       IRR_WT : in STD_LOGIC;
       IR_EN : in STD_LOGIC;
       ISR_ACCEPT : in STD_LOGIC;
       ISR_CLR : in std_logic;
       LEVEL : in STD_LOGIC;
       MASK : in STD_LOGIC;
       READ : in STD_LOGIC;
       RESET : in STD_LOGIC;
       D_OUT : out STD_LOGIC;
       IRR_N : out STD_LOGIC;
       ISR_O : out std_logic
  );
end Prior_cell;

architecture Prior_cell of Prior_cell is

---- Component declarations -----

component and2
  port (
       I0 : in STD_LOGIC;
       I1 : in STD_LOGIC;
       O : out STD_LOGIC
  );
end component;
component and2b1
  port (
       I0 : in STD_LOGIC;
       I1 : in STD_LOGIC;
       O : out STD_LOGIC
  );
end component;
component and3b1
  port (
       I0 : in STD_LOGIC;
       I1 : in STD_LOGIC;
       I2 : in STD_LOGIC;
       O : out STD_LOGIC
  );
end component;
component D_LATCH
  port (
       FREEZE : in STD_LOGIC;
       IRR_EN1 : in STD_LOGIC;
       RESET : in STD_LOGIC;
       IRR : out STD_LOGIC
  );
end component;
component fdce
  port (
       C : in STD_LOGIC;
       CE : in STD_LOGIC;
       CLR : in STD_LOGIC;
       D : in STD_LOGIC;
       Q : out STD_LOGIC
  );
end component;
component inv
  port (
       I0 : in STD_LOGIC;
       O : out STD_LOGIC
  );
end component;
component m2_1
  port (
       D0 : in STD_LOGIC;
       D1 : in STD_LOGIC;
       S0 : in STD_LOGIC;
       O : out STD_LOGIC
  );
end component;
component or2
  port (
       I1 : in std_logic;
       I2 : in std_logic;
       O : out std_logic
  );
end component;
component or3
  port (
       I0 : in STD_LOGIC;
       I1 : in STD_LOGIC;
       I2 : in STD_LOGIC;
       O : out STD_LOGIC
  );
end component;

----     Constants     -----
constant VCC_CONSTANT   : STD_LOGIC := '1';

signal AB1 : STD_LOGIC;
signal AB2 : std_logic;
signal CLR_IRR : STD_LOGIC;
signal CLR_ISR : std_logic;
signal IRR : STD_LOGIC;
signal IRR_EN1 : std_logic;
signal ISR_O_A : std_logic;
signal ISR_Q : STD_LOGIC;
signal NET3735 : std_logic;
signal NET5427 : std_logic;
signal NET5561 : std_logic;
signal NET6216 : STD_LOGIC;
signal NET6767 : STD_LOGIC;

---- Power signals declarations -----
signal VCC1 : STD_LOGIC;

begin

----  Component instantiations  ----

 U0 : fdce
  port map(
       C => IR_EN,
       CE => VCC1,
       CLR => CLR_IRR,
       D => VCC1,
       Q => AB1
  );

 U1 : or3
  port map(
       I0 => IMR,
       I1 => RESET,
       I2 => NET6767,
       O => CLR_IRR
  );

 U10 : or2
  port map(
       I1 => NET5427,
       I2 => NET5561,
       O => ISR_O_A
  );

 U11 : inv
  port map(
       I0 => ISR_Q,
       O => NET6216
  );

 U12 : and2b1
  port map(
       I0 => ISR_Q,
       I1 => MASK,
       O => NET5427
  );

 U13 : and3b1
  port map(
       I0 => IMR,
       I1 => ISR_Q,
       I2 => MASK,
       O => NET5561
  );

 U15 : and2
  port map(
       I0 => IRR_WT,
       I1 => ISR_ACCEPT,
       O => NET6767
  );

 U2 : and2b1
  port map(
       I0 => IRR,
       I1 => ISR_Q,
       O => IRR_N
  );

 U3 : or2
  port map(
       I1 => ISR_CLR,
       I2 => RESET,
       O => CLR_ISR
  );

 U4 : fdce
  port map(
       C => ISR_ACCEPT,
       CE => NET6216,
       CLR => CLR_ISR,
       D => IRR_WT,
       Q => ISR_Q
  );

 U5 : m2_1
  port map(
       D0 => IRR,
       D1 => ISR_Q,
       O => D_OUT,
       S0 => READ
  );

 U6 : D_LATCH
  port map(
       FREEZE => FREEZE,
       IRR => IRR,
       IRR_EN1 => IRR_EN1,
       RESET => RESET
  );

 U7 : or2
  port map(
       I1 => AB2,
       I2 => NET3735,
       O => IRR_EN1
  );

 U8 : and2b1
  port map(
       I0 => AB1,
       I1 => LEVEL,
       O => AB2
  );

 U9 : and3b1
  port map(
       I0 => IMR,
       I1 => IR_EN,
       I2 => LEVEL,
       O => NET3735
  );

---- Power , ground assignment ----

VCC1 <= VCC_CONSTANT;

---- Terminal assignment ----

    -- Output buffer terminals
    ISR_O <= ISR_O_A;

end Prior_cell;


------------------------------------------------------------------------------------
-- PR_CELL8 ---------------------------------------------------------------------
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity PR_CELL8 is port (
	IR : in STD_LOGIC_VECTOR (7 downto 0);
	IMR : in STD_LOGIC_VECTOR (7 downto 0);
	ISR_CLR : in STD_LOGIC_VECTOR (7 downto 0);
	IRR_WT : in STD_LOGIC_VECTOR (7 downto 0);