c_8259.vhd.txt

Vhdl硬件描述语言例子集

---------------------------------------------------------------------------
-- Copyright (c) 2002 by Aldec, Inc. All rights reserved.
--
---------------------------------------------------------------------------
-- DESIGN        :  C-8259
-- DESCRIPTION   :  Programmable interrupt controller
-- CREATED       :  2004-8-31, 22:56:10
---------------------------------------------------------------------------


------------------------------------------------------------------------------------
-- Multiplexer (two lines) ------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity M2_1 is port (
	D0 : in STD_LOGIC;
	D1 : in STD_LOGIC;
	O : out STD_LOGIC;
	S0 : in STD_LOGIC
);
end M2_1;

architecture SCHEMATIC of M2_1 is
begin
	O <= D0 when S0='0' else D1;
end SCHEMATIC;

------------------------------------------------------------------------------------
-- flip-flop latch with active rising edge clock --------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity FDCE is port (
	C : in STD_LOGIC;
	CE : in STD_LOGIC;
	CLR : in STD_LOGIC;
	D : in STD_LOGIC;
	Q : out STD_LOGIC
);
end FDCE;

architecture SCHEMATIC of FDCE is
begin

MAIN: process (C, CLR, CE, D) is
begin
	if CLR='1' then
		Q <= '0';
	elsif C'event and C='1' then
		if CE='1' then
			Q <= D;
		end if;
	end if;
end process MAIN;

end SCHEMATIC;


------------------------------------------------------------------------------------
-- three flip-flops with active rising edge clock ------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity FDCEx3 is port (
	I : in STD_LOGIC_VECTOR (2 downto 0);
	O : out STD_LOGIC_VECTOR (2 downto 0);
	C : in STD_LOGIC;
	CE : in STD_LOGIC;
	CLR : in STD_LOGIC
);
end FDCEx3;

architecture SCHEMATIC of FDCEx3 is
	component FDCE
	port(
		C : in std_logic;
		CE : in std_logic;
		CLR : in std_logic;
		D : in std_logic;
		Q : out std_logic);
	end component;
begin

--COMPONENT INSTANCES
FDCEx3_G: for N in 0 to 2 generate
	H1 : FDCE port map(
		C => C,
		CE => CE,
		CLR => CLR,
		D => I(N),
		Q => O(N)
	);
end generate;

end SCHEMATIC;

------------------------------------------------------------------------------------
-- eight flip-flops with active rising edge clock ------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity FDCEx8 is port (
	I : in STD_LOGIC_VECTOR (7 downto 0);
	O : out STD_LOGIC_VECTOR (7 downto 0);
	C : in STD_LOGIC;
	CE : in STD_LOGIC;
	CLR : in STD_LOGIC
);
end FDCEx8;

architecture SCHEMATIC of FDCEx8 is

	component FDCE
	port(
		C : in std_logic;
		CE : in std_logic;
		CLR : in std_logic;
		D : in std_logic;
		Q : out std_logic);
	end component;
begin

--COMPONENT INSTANCES

FDCEx8_G: for N in 0 to 7 generate
	H1 : FDCE port map(
		C => C,
		CE => CE,
		CLR => CLR,
		D => I(N),
		Q => O(N)
	);
end generate;
end SCHEMATIC;

------------------------------------------------------------------------------------
-- Barrel sShifter with 8 lines (rotate right) ------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity BRLSHFT8_R is port (
	I : in STD_LOGIC_VECTOR (7 downto 0);
	S : in STD_LOGIC_VECTOR (2 downto 0);
	O : out STD_LOGIC_VECTOR (7 downto 0)
);
end BRLSHFT8_R;

architecture BRLSHFT8_R of BRLSHFT8_R is

signal M01 : STD_LOGIC ;
signal M12 : STD_LOGIC ;
signal M23 : STD_LOGIC ;
signal M34 : STD_LOGIC ;
signal M45 : STD_LOGIC ;
signal M56 : STD_LOGIC ;
signal M67 : STD_LOGIC ;
signal M70 : STD_LOGIC ;
signal MO0 : STD_LOGIC ;
signal MO1 : STD_LOGIC ;
signal MO2 : STD_LOGIC ;
signal MO3 : STD_LOGIC ;
signal MO4 : STD_LOGIC ;
signal MO5 : STD_LOGIC ;
signal MO6 : STD_LOGIC ;
signal MO7 : STD_LOGIC ;

	component M2_1
	port(
		D0 : in std_logic;
		D1 : in std_logic;
		O : out std_logic;
		S0 : in std_logic);
	end component;

begin

----  Component instantiations  ----

U0 : M2_1
  port map(
       D0 => I(0),
       D1 => I(1),
       O => M01,
       S0 => S(0)
  );

U1 : M2_1
  port map(
       D0 => I(1),
       D1 => I(2),
       O => M12,
       S0 => S(0)
  );

U2 : M2_1
  port map(
       D0 => I(2),
       D1 => I(3),
       O => M23,
       S0 => S(0)
  );

U3 : M2_1
  port map(
       D0 => I(3),
       D1 => I(4),
       O => M34,
       S0 => S(0)
  );

U4 : M2_1
  port map(
       D0 => I(4),
       D1 => I(5),
       O => M45,
       S0 => S(0)
  );

U5 : M2_1
  port map(
       D0 => I(5),
       D1 => I(6),
       O => M56,
       S0 => S(0)
  );

U6 : M2_1
  port map(
       D0 => I(6),
       D1 => I(7),
       O => M67,
       S0 => S(0)
  );

U7 : M2_1
  port map(
       D0 => I(7),
       D1 => I(0),
       O => M70,
       S0 => S(0)
  );

U8 : M2_1
  port map(
       D0 => M70,
       D1 => M12,
       O => MO7,
       S0 => S(1)
  );

U9 : M2_1
  port map(
       D0 => M67,
       D1 => M01,
       O => MO6,
       S0 => S(1)
  );

U10 : M2_1
  port map(
       D0 => M56,
       D1 => M70,
       O => MO5,
       S0 => S(1)
  );

U11 : M2_1
  port map(
       D0 => M45,
       D1 => M67,
       O => MO4,
       S0 => S(1)
  );

U12 : M2_1
  port map(
       D0 => M34,
       D1 => M56,
       O => MO3,
       S0 => S(1)
  );

U13 : M2_1
  port map(
       D0 => M23,
       D1 => M45,
       O => MO2,
       S0 => S(1)
  );

U14 : M2_1
  port map(
       D0 => M12,
       D1 => M34,
       O => MO1,
       S0 => S(1)
  );

U15 : M2_1
  port map(
       D0 => M01,
       D1 => M23,
       O => MO0,
       S0 => S(1)
  );

U16 : M2_1
  port map(
       D0 => MO0,
       D1 => MO4,
       O => O(0),
       S0 => S(2)
  );

U17 : M2_1
  port map(
       D0 => MO1,
       D1 => MO5,
       O => O(1),
       S0 => S(2)
  );

U18 : M2_1
  port map(
       D0 => MO2,
       D1 => MO6,
       O => O(2),
       S0 => S(2)
  );

U19 : M2_1
  port map(
       D0 => MO3,
       D1 => MO7,
       O => O(3),
       S0 => S(2)
  );

U20 : M2_1
  port map(
       D0 => MO4,
       D1 => MO0,
       O => O(4),
       S0 => S(2)
  );

U21 : M2_1
  port map(
       D0 => MO5,
       D1 => MO1,
       O => O(5),
       S0 => S(2)
  );

U22 : M2_1
  port map(
       D0 => MO6,
       D1 => MO2,
       O => O(6),
       S0 => S(2)
  );

U23 : M2_1
  port map(
       D0 => MO7,
       D1 => MO3,
       O => O(7),
       S0 => S(2)
  );

end BRLSHFT8_R;

------------------------------------------------------------------------------------
-- Barrel Shifter with 8 lines (rotate left) -------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity BRLSHFT8_L is port (
	I : in STD_LOGIC_VECTOR (7 downto 0);
	S : in STD_LOGIC_VECTOR (2 downto 0);
	O : out STD_LOGIC_VECTOR (7 downto 0)
);
end BRLSHFT8_L;

architecture BRLSHFT8_L of BRLSHFT8_L is

signal M01 : STD_LOGIC ;
signal M12 : STD_LOGIC ;
signal M23 : STD_LOGIC ;
signal M34 : STD_LOGIC ;
signal M45 : STD_LOGIC ;
signal M56 : STD_LOGIC ;
signal M67 : STD_LOGIC ;
signal M70 : STD_LOGIC ;
signal MO0 : STD_LOGIC ;
signal MO1 : STD_LOGIC ;
signal MO2 : STD_LOGIC ;
signal MO3 : STD_LOGIC ;
signal MO4 : STD_LOGIC ;
signal MO5 : STD_LOGIC ;
signal MO6 : STD_LOGIC ;
signal MO7 : STD_LOGIC ;

---- Component declarations -----

component M2_1
  port (
       D0 : in STD_LOGIC;
       D1 : in STD_LOGIC;
       S0 : in STD_LOGIC;
       O : out STD_LOGIC
  );
end component ;

begin

----  Component instantiations  ----

U0 : M2_1
  port map(
       D0 => I(0),
       D1 => I(7),
       O => M01,
       S0 => S(0)
  );

U1 : M2_1
  port map(
       D0 => I(1),
       D1 => I(0),
       O => M12,
       S0 => S(0)
  );

U2 : M2_1
  port map(
       D0 => I(2),
       D1 => I(1),
       O => M23,
       S0 => S(0)
  );

U3 : M2_1
  port map(
       D0 => I(3),
       D1 => I(2),
       O => M34,
       S0 => S(0)
  );

U4 : M2_1
  port map(
       D0 => I(4),
       D1 => I(3),
       O => M45,
       S0 => S(0)
  );

U5 : M2_1
  port map(
       D0 => I(5),
       D1 => I(4),
       O => M56,
       S0 => S(0)
  );

U6 : M2_1
  port map(
       D0 => I(6),
       D1 => I(5),
       O => M67,
       S0 => S(0)
  );

U7 : M2_1
  port map(
       D0 => I(7),
       D1 => I(6),
       O => M70,
       S0 => S(0)
  );

U8 : M2_1
  port map(
       D0 => M70,
       D1 => M56,
       O => MO7,
       S0 => S(1)
  );

U9 : M2_1
  port map(
       D0 => M67,
       D1 => M45,
       O => MO6,
       S0 => S(1)
  );

U10 : M2_1
  port map(
       D0 => M56,
       D1 => M34,
       O => MO5,
       S0 => S(1)
  );

U11 : M2_1
  port map(
       D0 => M45,
       D1 => M23,
       O => MO4,
       S0 => S(1)
  );

U12 : M2_1
  port map(
       D0 => M34,
       D1 => M12,
       O => MO3,
       S0 => S(1)
  );

U13 : M2_1
  port map(
       D0 => M23,
       D1 => M01,
       O => MO2,
       S0 => S(1)
  );

U14 : M2_1
  port map(
       D0 => M12,
       D1 => M70,
       O => MO1,
       S0 => S(1)
  );

U15 : M2_1
  port map(
       D0 => M01,
       D1 => M67,