rtl8139.h

minix3的源码

#define		RL_TSAD_OWN3	0x0008	/* OWN bit of Descriptor 3 */
#define		RL_TSAD_OWN2	0x0004	/* OWN bit of Descriptor 2 */
#define		RL_TSAD_OWN1	0x0002	/* OWN bit of Descriptor 1 */
#define		RL_TSAD_OWN0	0x0001	/* OWN bit of Descriptor 0 */
#define RL_BMCR		0x62	/* Basic Mode Control Register (MII_CTRL) */
#define RL_BMSR		0x64	/* Basic Mode Status Register (MII_STATUS) */
#define	RL_ANAR		0x66	/* Auto-Neg Advertisement Register (MII_ANA) */
#define	RL_ANLPAR	0x68	/* Auto-Neg Link Partner Register (MII_ANLPA) */
#define	RL_ANER		0x6a	/* Auto-Neg Expansion Register (MII_ANE) */
#define	RL_NWAYTR	0x70	/* N-way Test Register */
#define	RL_CSCR		0x74	/* CS Configuration Register */
#define RL_CONFIG5	0xD8	/* Configuration Register 5 */

/* Status word in receive buffer */
#define RL_RXS_LEN_M	0xFFFF0000	/* Length Field, Excl. Status word */
#define RL_RXS_LEN_S	16		/* Shift For Length */
#define RL_RXS_MAR	0x00008000	/* Multicast Address Received */
#define RL_RXS_PAR	0x00004000	/* Physical Address Matched */
#define RL_RXS_BAR	0x00002000	/* Broadcast Address Received */
#define RL_RXS_RES_M	0x00001FC0	/* Reserved */
#define RL_RXS_ISE	0x00000020	/* Invalid Symbol Error */
#define RL_RXS_RUNT	0x00000010	/* Runt Packet Received */
#define RL_RXS_LONG	0x00000008	/* Long (>4KB) Packet */
#define RL_RXS_CRC	0x00000004	/* CRC Error */
#define RL_RXS_FAE	0x00000002	/* Frame Alignment Error */
#define RL_RXS_ROK	0x00000001	/* Receive OK */

/* Registers in the Machine Independent Interface (MII) to the PHY.
 * IEEE 802.3 (2000 Edition) Clause 22.
 */
#define MII_CTRL	0x0	/* Control Register (basic) */
#define		MII_CTRL_RST	0x8000	/* Reset PHY */
#define		MII_CTRL_LB	0x4000	/* Enable Loopback Mode */
#define		MII_CTRL_SP_LSB	0x2000	/* Speed Selection (LSB) */
#define		MII_CTRL_ANE	0x1000	/* Auto Negotiation Enable */
#define		MII_CTRL_PD	0x0800	/* Power Down */
#define		MII_CTRL_ISO	0x0400	/* Isolate */
#define		MII_CTRL_RAN	0x0200	/* Restart Auto-Negotiation Process */
#define		MII_CTRL_DM	0x0100	/* Full Duplex */
#define		MII_CTRL_CT	0x0080	/* Enable COL Signal Test */
#define		MII_CTRL_SP_MSB	0x0040	/* Speed Selection (MSB) */
#define			MII_CTRL_SP_10		0x0000	/* 10 Mb/s */
#define			MII_CTRL_SP_100		0x2000	/* 100 Mb/s */
#define			MII_CTRL_SP_1000	0x0040	/* 1000 Mb/s */
#define			MII_CTRL_SP_RES		0x2040	/* Reserved */
#define		MII_CTRL_RES	0x003F	/* Reserved */
#define MII_STATUS	0x1	/* Status Register (basic) */
#define		MII_STATUS_100T4	0x8000	/* 100Base-T4 support */
#define		MII_STATUS_100XFD	0x4000	/* 100Base-X FD support */
#define		MII_STATUS_100XHD	0x2000	/* 100Base-X HD support */
#define		MII_STATUS_10FD		0x1000	/* 10 Mb/s FD support */
#define		MII_STATUS_10HD		0x0800	/* 10 Mb/s HD support */
#define		MII_STATUS_100T2FD	0x0400	/* 100Base-T2 FD support */
#define		MII_STATUS_100T2HD	0x0200	/* 100Base-T2 HD support */
#define		MII_STATUS_EXT_STAT	0x0100	/* Supports MII_EXT_STATUS */
#define		MII_STATUS_RES		0x0080	/* Reserved */
#define		MII_STATUS_MFPS		0x0040	/* MF Preamble Suppression */
#define		MII_STATUS_ANC		0x0020	/* Auto-Negotiation Completed */
#define		MII_STATUS_RF		0x0010	/* Remote Fault Detected */
#define		MII_STATUS_ANA		0x0008	/* Auto-Negotiation Ability */
#define		MII_STATUS_LS		0x0004	/* Link Up */
#define		MII_STATUS_JD		0x0002	/* Jabber Condition Detected */
#define		MII_STATUS_EC		0x0001	/* Ext Register Capabilities */
#define MII_PHYID_H	0x2	/* PHY ID (high) */
#define MII_PHYID_L	0x3	/* PHY ID (low) */
#define MII_ANA		0x4	/* Auto-Negotiation Advertisement */
#define		MII_ANA_NP	0x8000	/* Next PAge */
#define		MII_ANA_RES	0x4000	/* Reserved */
#define		MII_ANA_RF	0x2000	/* Remote Fault */
#define		MII_ANA_TAF_M	0x1FE0	 /* Technology Ability Field */
#define		MII_ANA_TAF_S	5	 /* Shift */
#define			MII_ANA_TAF_RES		0x1000	/* Reserved */
#define			MII_ANA_PAUSE_ASYM	0x0800	/* Asym. Pause */
#define			MII_ANA_PAUSE_SYM	0x0400	/* Sym. Pause */
#define			MII_ANA_100T4		0x0200	/* 100Base-T4 */
#define			MII_ANA_100TXFD		0x0100	/* 100Base-TX FD */
#define			MII_ANA_100TXHD		0x0080	/* 100Base-TX HD */
#define			MII_ANA_10TFD		0x0040	/* 10Base-T FD */
#define			MII_ANA_10THD		0x0020	/* 10Base-T HD */
#define		MII_ANA_SEL_M	0x001F	 /* Selector Field */
#define			MII_ANA_SEL_802_3 0x0001 /* 802.3 */
#define MII_ANLPA	0x5	/* Auto-Neg Link Partner Ability Register */
#define		MII_ANLPA_NP	0x8000	/* Next Page */
#define		MII_ANLPA_ACK	0x4000	/* Acknowledge */
#define		MII_ANLPA_RF	0x2000	/* Remote Fault */
#define		MII_ANLPA_TAF_M	0x1FC0	 /* Technology Ability Field */
#define		MII_ANLPA_SEL_M	0x001F	 /* Selector Field */
#define MII_ANE		0x6	/* Auto-Negotiation Expansion */
#define		MII_ANE_RES	0xFFE0	/* Reserved */
#define		MII_ANE_PDF	0x0010	/* Parallel Detection Fault */
#define		MII_ANE_LPNPA	0x0008	/* Link Partner is Next Page Able */
#define		MII_ANE_NPA	0x0002	/* Local Device is Next Page Able */
#define		MII_ANE_PR	0x0002	/* New Page has been received */
#define		MII_ANE_LPANA	0x0001	/* Link Partner is Auto-Neg.able */
#define MII_ANNPT	0x7	/* Auto-Negotiation Next Page Transmit */
#define MII_ANLPRNP	0x8	/* Auto-Neg Link Partner Received Next Page */
#define MII_MS_CTRL	0x9	/* MASTER-SLAVE Control Register */
#define MII_MS_STATUS	0xA	/* MASTER-SLAVE Status Register */
/* 0xB ... 0xE */		/* Reserved */
#define MII_EXT_STATUS	0xF	/* Extended Status */
#define		MII_ESTAT_1000XFD	0x8000	/* 1000Base-X Full Duplex */
#define		MII_ESTAT_1000XHD	0x4000	/* 1000Base-X Half Duplex */
#define		MII_ESTAT_1000TFD	0x2000	/* 1000Base-T Full Duplex */
#define		MII_ESTAT_1000THD	0x1000	/* 1000Base-T Half Duplex */
#define		MII_ESTAT_RES		0x0FFF	/* Reserved */
/* 0x10 ... 0x1F */		/* Vendor Specific */

#if 0
34-35	R	ERBCR		Early Receive (Rx) Byte Count Register
36	R	ERSR		Early Rx Status Register
	7-4			reserved
	3	R	ERGood	Early Rx Good packet
	2	R	ERBad	Early Rx Bad packet
	1	R	EROVW	Early Rx OverWrite
	0	R	EROK	Early Rx OK
51	R/W	CONFIG0		Configuration Register 0
	7	R	SCR	Scrambler Mode
	6	R	PCS	PCS Mode
	5	R	T10	10 Mbps Mode
	4-3	R	PL[1-0]	Select 10 Mbps medium type
	2-0	R	BS[2-0]	Select Boot ROM size
52	R/W	CONFIG1		Configuration Register 1
	7-6	R/W	LEDS[1-0] LED PIN
	5	R/W	DVRLOAD	Driver Load
	4	R/W	LWACT	LWAKE active mode
	3	R	MEMMAP	Memory Mapping
	2	R	IOMAP	I/O Mapping
	1	R/W	VPD	Set to enable Vital Product Data
	0	R/W	PMEn	Power Management Enable
59	R/W	CONFIG3		Configuration Register 3
	7	R	GNTSel	Gnt Select
	6	R/W	PARM_En	Parameter Enable
	5	R/W	Magic	Magic Packet
	4	R/W	LinkUp	Link Up
	3			reserved
	2	R	CLKRUN_En CLKRUN Enable
	1			reserved
	0	R	FBtBEn	Fast Back to Back Enable
5a	R/W	CONFIG4		Configuration Register 4
	7	R/W	RxFIFOAutoClr Auto Clear the Rx FIFO on overflow
	6	R/W	AnaOff	Analog Power Off
	5	R/W	LongWF	Long Wake-up Frame
	4	R/W	LWPME	LANWAKE vs PMEB
	3			reserved
	2	R/W	LWPTN	LWAKE pattern
	1			reserved
	0	R/W	PBWakeup Pre-Boot Wakeup
5c-5d	R/W	MULINT		Multiple Interrupt Select
	15-12			reserved
	11-0	R/W	MISR[11-0] Multiple Interrupt Select
68-69	R	ANLPAR		Auto-Negotiation Link Partnet Register
	15	R	NP	Next Page bit
	14	R	ACK	acknowledge received from link partner
	13	R/W	RF	received remote fault detection capability
	12-11			reserved
	10	R	Pause	Flow control is supported
	9	R	T4	100Base-T4 is supported
	8	R/W	TXFD	100Base-TX full duplex is supported
	7	R/W	TX	100Base-TX is supported
	6	R/W	10FD	10Base-T full duplex is supported
	5	R/W	10	10Base-T is supported
	4-0	R/W	Selector Binary encoded selector
6a-6b	R	ANER		Auto-Negotiation Expansion Register
	15-5			reserved
	4	R	MLF	Multiple link fault occured
	3	R	LP_NP_ABLE Link partner supports Next Page
	2	R	NP_ABLE	Local node is able to send add. Next Pages
	1	R	PAGE_RX	Link Code Word Page received
	0	R	LP_NW_ABLE Link partner supports NWay auto-negotiation
70-71	R/W	NWAYTR		N-way Test Register
	15-8			reserved
	7	R/W	NWLPBK	NWay loopback mode
	6-4			reserved
	3	R	ENNWLE	LED0 pin indicates linkpulse
	2	R	FLAGABD	Auto-neg experienced ability detect state
	1	R	FLAGPDF	Auto-neg exp. par. detection fault state
	0	R	FLAGLSC	Auto-neg experienced link status check state
74-75	R/W	CSCR		CS Configuration Register
	15	W	Testfun	Auto-neg speeds up internal timer
	14-10			reserved
	9	R/W	LD	Active low TPI link disable signal
	8	R/W	HEARTBEAT HEART BEAT enable
	7	R/W	JBEN	Enable jabber function
	6	R/W	F_LINK_100 Force 100 Mbps
	5	R/W	F_Conect Bypass disconnect function
	4			reserved
	3	R	Con_status Connected link detected
	2	R/W	Con_status_En Configures LED1 to indicate conn. stat.
	1			reserved
	0	R/W	PASS_SCR Bypass scramble
76-77				reserved
78-7b	R/W	PHY1_PARM	PHY parameter 1
7c-7f	R/W	TW_PARM		Twister parameter
80	R/W	PHY2_PARM	PHY parameter 2
81-83				reserved
84-8b	R/W	CRC[0-7]	Power Management CRC reg.[0-7] for frame[0-7]
8c-cb	R/W	Wakeup[0-7]	Power Management wakeup frame[0-7] (64 bit)
cc-d3	R/W	LSBCRC[0-7]	LSB of the mask byte of makeup frame[0-7]
d4-d7				reserved
d8	R/W	Config5		Configuration register 5
	7			reserved
	6	R/W	BWF	Broadcast Wakeup Frame
	5	R/W	MWF	Multicast Wakeup Frame
	4	R/W	UWF	Unicast Wakeup Frame
	3	R/W	FifoAddrPtr FIFO Address Pointer
	2	R/W	LDPS	Link Down Power Saving mode
	1	R/W	LANWake	LANWake Signal
	0	R/W	PME_STS	PME_Status bit
d9-ff				reserved
#endif

/*
 * $PchId: rtl8139.h,v 1.1 2003/09/05 10:58:50 philip Exp $
 */