vrs51l3074_keil.h

this a c program,be careful

sfr AURES1         = 0xB5;     // Arithmetic Unit Result 1                                                  
sfr AURES2         = 0xB6;     // Arithmetic Unit Result 2                                                  
sfr AURES3         = 0xB7;     // Arithmetic Unit Result 3                                                  

sfr AUSHIFTCFG     = 0xC1;     // Arithmetic Unit shift configuration                                       
sfr AUCONFIG1      = 0xC2;     // Arithmetic Unit configuration 1                                           
sfr AUCONFIG2      = 0xC3;     // Arithmetic Unit configuration 2                                           
sfr AUPREV0        = 0xC4;     // Arithmetic Unit previous result 0                                         
sfr AUPREV1        = 0xC5;     // Arithmetic Unit previous result 1                                         
sfr AUPREV2        = 0xC6;     // Arithmetic Unit previous result 2                                         
sfr AUPREV3        = 0xC7;     // Arithmetic Unit previous result 3                                         

// SBIT definitions for bit addressable registers

// P0 (Address 0x80)
sbit P0_0          = 0x80;
sbit P0_1          = 0x81;
sbit P0_2          = 0x82;
sbit P0_3          = 0x83;
sbit P0_4          = 0x84;
sbit P0_5          = 0x85;
sbit P0_6          = 0x86;
sbit P0_7          = 0x87;

// INTEN1 (Address 0x88)
sbit SPITXEIEN     = 0x89;     // SPI TX Empty Interrupt Enable
sbit SPIRXOVIEN    = 0x8A;     // SPI Interrupt Enable / Rx Available / Rx Overrun
sbit T0IEN         = 0x8B;     // Timer 0 Interrupt Enable
sbit PCHGIEN0      = 0x8C;     // Port Change Interrupt Module 0 Enable
sbit U0IEN         = 0x8D;     // UART 0 Interrupt Enable
sbit U1IEN         = 0x8E;     // UART 1 Interrupt Enable
sbit T1IEN         = 0x8F;     // Timer 1 Interrupt Enable

// P1 (Address 0x90)
sbit P1_0          = 0x90;
sbit P1_1          = 0x91;
sbit P1_2          = 0x92;
sbit P1_3          = 0x93;
sbit P1_4          = 0x94;
sbit P1_5          = 0x95;
sbit P1_6          = 0x96;
sbit P1_7          = 0x97;

// P5 (Address 0x98)
sbit P5_0          = 0x98;
sbit P5_1          = 0x99;
sbit P5_2          = 0x9A;
sbit P5_3          = 0x9B;
sbit P5_4          = 0x9C;
sbit P5_5          = 0x9D;
sbit P5_6          = 0x9E;
sbit P5_7          = 0x9F;

// P2 (Address 0xA0)
sbit P2_0          = 0xA0;
sbit P2_1          = 0xA1;
sbit P2_2          = 0xA2;
sbit P2_3          = 0xA3;
sbit P2_4          = 0xA4;
sbit P2_5          = 0xA5;
sbit P2_6          = 0xA6;
sbit P2_7          = 0xA7;

// INTEN2 (Address 0xA8)
sbit T2IEN         = 0xA8;     // Timer 2 Interrupt Enable
sbit I2CIEN        = 0xA9;     // I2C Interrupt Enable
sbit I2CUARTCI     = 0xAA;
sbit PWCIEN        = 0xAB;     // Pulse Width Counter Interrupt Enable
sbit PWMT03IEN     = 0xAC;     // PWM as Timer 0-3 Overflow Interrupt Enable
sbit PWMT47IEN     = 0xAD;     // PWM as Timer 4-7 Overflow Interrupt Enable
sbit AUWDTIEN      = 0xAE;     // Watchdog Timer / Arithmatic Unit Interrupt Enable
sbit PCHGIEN1      = 0xAF;     // Port Change Interrupt Module 1 Enable

// P3 (Address 0xB0)
sbit P3_0          = 0xB0;
sbit P3_1          = 0xB1;
sbit P3_2          = 0xB2;
sbit P3_3          = 0xB3;
sbit P3_4          = 0xB4;
sbit P3_5          = 0xB5;
sbit P3_6          = 0xB6;
sbit P3_7          = 0xB7;

// IPINFLAG1 (Address 0xB8)
sbit INT0IF        = 0xB8;     // Interrupt 0 Flag
sbit INT1IF        = 0xB9;     // Interrupt 1 Flag
sbit P30IF         = 0xBA;     // P3.0 Interrupt Flag
sbit P31IF         = 0xBB;     // P3.1 Interrupt Flag
sbit P34IF         = 0xBC;     // P3.4 Interrupt Flag
sbit P35IF         = 0xBD;     // P3.5 Interrupt Flag
sbit P36IF         = 0xBE;     // P3.6 Interrupt Flag
sbit P37IF         = 0xBF;     // P3.7 Interrupt Flag

// P4 (Address 0xC0)
sbit P4_0          = 0xC0;
sbit P4_1          = 0xC1;
sbit P4_2          = 0xC2;
sbit P4_3          = 0xC3;
sbit P4_4          = 0xC4;
sbit P4_5          = 0xC5;
sbit P4_6          = 0xC6;
sbit P4_7          = 0xC7;

// P6 (Address 0xC8)
sbit P6_0          = 0xC8;
sbit P6_1          = 0xC9;
sbit P6_2          = 0xCA;
sbit P6_3          = 0xCB;
sbit P6_4          = 0xCC;
sbit P6_5          = 0xCD;
sbit P6_6          = 0xCE;
sbit P6_7          = 0xCF;

// PSW (Address 0xD0)
sbit P             = 0xD0;     // Parity Flag
sbit F1            = 0xD1;     // General Purpose Flag 1
sbit OV            = 0xD2;     // Overflow Flag
sbit RS0           = 0xD3;     // Register Bank Select 0
sbit RS1           = 0xD4;     // Register Bank Select 1
sbit F0            = 0xD5;     // General Purpose Flag 0
sbit AC            = 0xD6;     // Auxiliary Carry Bit Flag
sbit CY            = 0xD7;     // Carry Bit Flag

// IPINFLAG2 (Address 0xD8)
sbit P00IF         = 0xD8;     // P0.0 Interrupt Flag
sbit P01IF         = 0xD9;     // P0.1 Interrupt Flag
sbit P02IF         = 0xDA;     // P0.2 Interrupt Flag
sbit P03IF         = 0xDB;     // P0.3 Interrupt Flag
sbit P04IF         = 0xDC;     // P0.4 Interrupt Flag
sbit P05IF         = 0xDD;     // P0.5 Interrupt Flag
sbit P06IF         = 0xDE;     // P0.6 Interrupt Flag
sbit P07IF         = 0xDF;     // P0.7 Interrupt Flag

// ACC (Address 0xE0)
sbit ACC_0         = 0xE0;
sbit ACC_1         = 0xE1;
sbit ACC_2         = 0xE2;
sbit ACC_3         = 0xE3;
sbit ACC_4         = 0xE4;
sbit ACC_5         = 0xE5;
sbit ACC_6         = 0xE6;
sbit ACC_7         = 0xE7;

// B (Address 0xF0)
sbit B_0           = 0xF0;
sbit B_1           = 0xF1;
sbit B_2           = 0xF2;
sbit B_3           = 0xF3;
sbit B_4           = 0xF4;
sbit B_5           = 0xF5;
sbit B_6           = 0xF6;
sbit B_7           = 0xF7;

// USERFLAGS (Address 0xF8)
sbit UF_0          = 0xF8;
sbit UF_1          = 0xF9;
sbit UF_2          = 0xFA;
sbit UF_3          = 0xFB;
sbit UF_4          = 0xFC;
sbit UF_5          = 0xFD;
sbit UF_6          = 0xFE;
sbit UF_7          = 0xFF;

#endif
/**************************************************************************
* Copyright (C) 2007 Ramtron International Corporation
**************************************************************************/