starto.s

来自「国产CPU－龙芯（loongson)BIOS源代码」· S 代码 · 共 2,687 行 · 第 1/4 页

	srl	t0,t3,20
	sub	t0,1
	sw	t0, SCS_2_HIGH_DECODE_ADDRESS(s2)
	b	done_dens	
	move	s1,t3

1:
	addu	t1,s1,t3
	TTYDBG("t1=");
	bal	hexserial
	move	a0,t1
	TTYDBG("\r\n");

	bgtu	t1, 0x10000000,2f
	nop
	srl	t0,s1,20
	sw	t0, SCS_2_LOW_DECODE_ADDRESS(s2)
	srl	t0,t1,20
	sub	t0, 1
	sw	t0, SCS_2_HIGH_DECODE_ADDRESS(s2)
	b 	done_dens
	move	s1,t1
2:

	bgtu	s1,HIGHMEM_BASE,3f
	nop
	TTYDBG("s1=");
	li	s1,HIGHMEM_BASE
	bal 	hexserial
	move	a0,s1
	TTYDBG("\r\n");
3:
	addu 	t1,s1,t3

	TTYDBG("HIGT=");
	bal	hexserial
	move	a0,t1
	TTYDBG("\r\n");


	srl	t0,s1,20
	sw	t0, SCS_2_LOW_DECODE_ADDRESS(s2)
	srl	t0,t1,20
	sub	t0, 1
	sw	t0, SCS_2_HIGH_DECODE_ADDRESS(s2)
	b 	done_dens
	move	s1,t1	

sdram_slot1_2bank:
	TTYDBG("DIMM1: 2 sides\r\n");
	bnez	s1,1f
	nop
	bgtu	t3, 0x20000000, panic_dimm1_too_big
	nop
	
	bgtu 	t3, 0x10000000,2f
	nop
	li	t0, 0
	sw	t0, SCS_0_LOW_DECODE_ADDRESS(s2)
	srl	t0, t3, 21
	sw	t0, SCS_1_LOW_DECODE_ADDRESS(s2)

	sub	t0, 1
	sw	t0, SCS_0_HIGH_DECODE_ADDRESS(s2)
	srl	t0, t3, 20
	sub	t0, 1
	sw	t0, SCS_1_HIGH_DECODE_ADDRESS(s2)
	b	done_dens	
	move 	s1,t3
2:
	li	t0,0
	sw	t0, SCS_0_LOW_DECODE_ADDRESS(s2)
	srl	t0,t3,21
	sub	t0,1
	sw	t0, SCS_0_HIGH_DECODE_ADDRESS(s2)
	
	li	t0,HIGHMEM_BASE
	
	srl	t1,t3,1
	sw	t0, SCS_1_LOW_DECODE_ADDRESS(s2)
	addu	t1,t1,t0
	srl	t0,t1,20
	sub	t0,1
	sw	t0, SCS_1_HIGH_DECODE_ADDRESS(s2)
	b	done_dens
	move	s1,t1
1:
	srl	t1,t3,1
	addu	t1,s1
	bgtu	t1, 0x10000000, 2f
	nop
	srl	t0,s1,20
	sw	t0, SCS_2_LOW_DECODE_ADDRESS(s2)
	srl	t0,t1,20
	sub	t0,1		
	sw	t0, SCS_2_HIGH_DECODE_ADDRESS(s2)
	move	s1,t1
	srl	t1,t3,1
	addu	t1,s1
	bgtu	t1,0x10000000,4f
	nop
	srl	t0,s1,20
	sw	t0, SCS_3_LOW_DECODE_ADDRESS(s2)
	srl	t0,t1,20
	sub	t0,1		
	sw	t0, SCS_3_HIGH_DECODE_ADDRESS(s2)
	move	s1,t1
	b	done_dens
	nop	
2:
	bgtu	s1,HIGHMEM_BASE,3f
	nop
	li	s1,HIGHMEM_BASE
3:
	srl	t1,t3,1
	addu	t1,s1
	srl	t0, s1, 20
	sw	t0, SCS_2_LOW_DECODE_ADDRESS(s2)
	srl	t0, t1, 20
	sw	t0, SCS_3_LOW_DECODE_ADDRESS(s2)
	sub	t0, 1
	sw	t0, SCS_2_HIGH_DECODE_ADDRESS(s2)
	addu	t0, s1, t3
	srl	t0, t0, 20
	sub	t0, 1
	sw	t0, SCS_3_HIGH_DECODE_ADDRESS(s2)
	b	done_dens	
	addu	s1,t3
4:
	bgtu	s1,HIGHMEM_BASE,5f
	nop
	li	s1,HIGHMEM_BASE
5:
	srl 	t1,t3,1
	addu	t1,s1
	srl	t0,s1,20
	sw	t0, SCS_3_LOW_DECODE_ADDRESS(s2)
	srl	t0,t1,20
	sub 	t0,1
	sw	t0, SCS_3_LOW_DECODE_ADDRESS(s2)
	move	s1,t1
	
done_dens:
#ifdef RUN_SDRAM_FAST
	li	t0, HTOLE32(0x00e0c200)		/* non-registred */
#else
	li	t0, HTOLE32(0x04e0c080)		/* non-registred */
#endif
set_conf:
	sw	t0, SDRAM_CONFIGURATION(s2)

	li	t0, HTOLE32(2)
	sw	t0, SDRAM_ADDRESS_DECODE(s2)
	sw	zero, SDRAM_OPERATION_MODE(s2)
#ifdef	RUN_SDRAM_FAST
	/* MRS command issue */
	li	t0, HTOLE32(3)
	sw	t0, SDRAM_OPERATION_MODE(s2)
	lw	t0, SDRAM_OPERATION_MODE(s2)
	/* dummy write */
	li	t0, 0xa0000000
	sw	zero, 0(t0)
1:
	lw	t0, SDRAM_OPERATION_MODE(s2)
	and	t0, 0x80000000
	beqz	t0, 1b
	nop
	/* MRS command issue */
	li	t0, HTOLE32(3)
	sw	t0, SDRAM_OPERATION_MODE(s2)
	lw	t0, SDRAM_OPERATION_MODE(s2)
	/* dummy write */
	li	t0, 0xa0000000 + 1024*1024*64
	sw	zero, 0(t0)
1:
	lw	t0, SDRAM_OPERATION_MODE(s2)
	and	t0, 0x80000000
	beqz	t0, 1b
	nop

#endif	
	sw	zero, SDRAM_OPERATION_MODE(s2)
	lw	t0, SDRAM_OPERATION_MODE(s2)
	
	b	2f
	nop
#ifdef SKIPDIMM
skipdimm:
	li	t0, 0x0000007f
	sw	t0, SCS_0_HIGH_DECODE_ADDRESS(s2)
	sw	zero, SCS_0_LOW_DECODE_ADDRESS(s2)
	li	t0, 0x000000ff
	sw	t0, SCS_1_HIGH_DECODE_ADDRESS(s2)
	li	t0, 0x00000080
	sw	t0, SCS_1_LOW_DECODE_ADDRESS(s2)

	li	t0, 0x00008000
	sw	t0, SDRAM_BANK0PARAMETERS(s2)
	sw	t0, SDRAM_BANK1PARAMETERS(s2)
	li	t0, HTOLE32(0x04e0c080)		/* non-registred */
	sw	t0, SDRAM_CONFIGURATION(s2)

#ifdef	SDRAM_MODE_FIX
	li	t0, HTOLE32(2)
	sw	t0, SDRAM_ADDRESS_DECODE(s2)
	/* MRS command issue */
	li	t0, HTOLE32(3)
	sw	t0, SDRAM_OPERATION_MODE(s2)
	lw	t0, SDRAM_OPERATION_MODE(s2)
	/* dummy write */
	li	t0, 0xa0000000
	sw	zero, 0(t0)
1:
	lw	t0, SDRAM_OPERATION_MODE(s2)
	and	t0, 0x80000000
	beqz	t0, 1b
	nop

	/* MRS command issue */
	li	t0, HTOLE32(3)
	sw	t0, SDRAM_OPERATION_MODE(s2)
	lw	t0, SDRAM_OPERATION_MODE(s2)
	/* dummy write */
	li	t0, 0xa0000000 + 1024*1024*128
	sw	zero, 0(t0)
1:
	lw	t0, SDRAM_OPERATION_MODE(s2)
	and	t0, 0x80000000
	beqz	t0, 1b
	nop
#endif
	sw	zero, SDRAM_OPERATION_MODE(s2)
	lw	t0, SDRAM_OPERATION_MODE(s2)
	
	b	2f
	nop
#endif	
panic_dimm0_too_big:
	PRINTSTR("\r\nPANIC! DIMM0 cannot exceed 256MB\r\n")
	b	1f
panic_dimm1_too_big:
	PRINTSTR("\r\nPANIC! DIMM1 cannot exceed 256MB if DIMM0 is absent\r\n")
	b	1f
panic_no_memory:
	PRINTSTR("\r\nPANIC! No SDRAM installed\r\n")
1:
	b	1b
	nop

2:

	TTYDBG("Dumping SDRAM registers...\r\n");
	
	
	TTYDBG("SDRAM_CONFIGURATION=");
	bal	hexserial
	lw	a0, SDRAM_CONFIGURATION(s2)

	TTYDBG("\r\nSDRAM_TIMING_PARAMETERS=");
	bal	hexserial
	lw	a0, SDRAM_TIMING_PARAMETERS(s2)

	TTYDBG("\r\nSDRAM_BANK0PARAMETERS=");
	bal	hexserial
	lw	a0, SDRAM_BANK0PARAMETERS(s2)

	TTYDBG("\r\nSDRAM_BANK1PARAMETERS=");
	bal	hexserial
	lw	a0, SDRAM_BANK1PARAMETERS(s2)

	TTYDBG("\r\nSDRAM_BANK2PARAMETERS=");
	bal	hexserial
	lw	a0, SDRAM_BANK2PARAMETERS(s2)
	
	TTYDBG("\r\nSDRAM_BANK3PARAMETERS=");
	bal	hexserial
	lw	a0, SDRAM_BANK3PARAMETERS(s2)
	
	TTYDBG("\r\nSCS_0=");
	bal	hexserial
	lw	a0, SCS_0_LOW_DECODE_ADDRESS(s2)
	TTYDBG("~");
	bal	hexserial
	lw	a0, SCS_0_HIGH_DECODE_ADDRESS(s2)

	TTYDBG("\r\nSCS_1=");
	bal	hexserial
	lw	a0, SCS_1_LOW_DECODE_ADDRESS(s2)
	TTYDBG("~");
	bal	hexserial
	lw	a0, SCS_1_HIGH_DECODE_ADDRESS(s2)

	TTYDBG("\r\nSCS_2=");
	bal	hexserial
	lw	a0, SCS_2_LOW_DECODE_ADDRESS(s2)
	TTYDBG("~");
	bal	hexserial
	lw	a0, SCS_2_HIGH_DECODE_ADDRESS(s2)

	TTYDBG("\r\nSCS_3=");
	bal	hexserial
	lw	a0, SCS_3_LOW_DECODE_ADDRESS(s2)
	TTYDBG("~");
	bal	hexserial
	lw	a0, SCS_3_HIGH_DECODE_ADDRESS(s2)
	
	TTYDBG("\r\n");

/*
 *  Clear out 2Mb of memory (maximum cache size)
 */

	TTYDBG("Clearing cache size memory...\r\n");

	la	t0, UNCACHED_MEMORY_ADDR
	addu	t1, t0, 2*1024*1024
1:
	addu	t0, 8
	bne	t1, t0, 1b
	sd	zero, -8(t0)

	TTYDBG("Init SDRAM Done!\r\n");
	b	do_caches
	nop

in_ram:
	PRINTSTR("RAM loaded\r\n");
/*
 *  Reset and initialize caches to a known state.
 */
#define IndexStoreTagI	0x08
#define IndexStoreTagD	0x09
#define IndexStoreTagS	0x0b
#define IndexStoreTagT	0x0a
#define FillI		0x14

/*
 *  RM7000 config register bits.
 */
#define CF_7_SE         (1 << 3)        /* Secondary cache enable */
#define CF_7_SC         (1 << 31)       /* Secondary cache not present */
#define CF_7_TE         (1 << 12)       /* Tertiary cache enable */
#define CF_7_SCD	(1 << 13)	/* extend DCE interface signal by one cycle in the CPU */
#define CF_7_TC         (1 << 17)       /* Tertiary cache not present */
#define CF_7_TS         (3 << 20)       /* Tertiary cache size */
#define CF_7_TS_AL      20              /* Shift to align */
#define	GT_CPU_R7KL3	(1 << 14)	/* R7KL3 present*/
#define NOP8 nop;nop;nop;nop;nop;nop;nop;nop
do_caches:
	TTYDBG("Sizing caches...\r\n");

	mfc0	t3, COP_0_CONFIG	/* t3 = original config */
	and	t3, 0xffffeff0		/* Make sure coherency is OK */

	and	t3, ~(CF_7_TE|CF_7_SE|CF_7_TC|CF_7_SC)  /* disable L2/L3 cache */
	mtc0    t3, COP_0_CONFIG

	li	t2, 4096

	srl	t1, t3, 9
	and	t1, 7
	sllv	s3, t2, t1		/* s3 = I cache size */

#ifdef CONFIG_CACHE_64K_4WAY
	sll 	s3,2
#endif

	and	t1, t3, 0x20
	srl	t1, t1, 1
	addu	s4, t1, 16		/* s4 = I cache line size */

	srl	t1, t3, 6
	and	t1, 7
	sllv	s5, t2, t1		/* s5 = D cache size */

#ifdef CONFIG_CACHE_64K_4WAY
	sll 	s5,2
#endif

	and	t1, t3, 0x10
	addu	s6, t1, 16		/* s6 = D cache line size */
	TTYDBG("Init caches...\r\n")

	li	s7, 0                   /* no L2 cache */
	li	s8, 0                   /* no L3 cache */

	mfc0    a0, COP_0_PRID
	and 	a0, a0, 0xff00
	li      a1, 0x6300
	bne     a0,a1,1f
	nop
	TTYDBG("godson2 caches found\r\n")
        bal     godson2_cache_init
        nop

#ifdef CONFIG_GODSON_SECONDARY_CACHE

	li	s7, 0x200000

	TTYDBG("Init Godson L3 cache...\r\n")
                                                                                                                                                            
        or      t3, (CF_7_TE|CF_7_SCD)          /* Enable secondary cache */
        mtc0    t3, COP_0_CONFIG
        NOP8
	lw	t0, CPU_CONF(s2)
	or	t0, GT_CPU_R7KL3		/* Enable R7KL3 */
	sw	t0, CPU_CONF(s2)		
	
        li      a0, 0
        add     a1, a0, s7                      /* End = size of L2 cache */
1:	
	bal	invalidate_external_cache_page
	nop
	addu 	a0, a0, 4096
	bne	a0, a1, 1b
	nop                                                                                                                                   
#endif
	
	b	cache_done
	nop
1:

#if 0

	and	t1, t3, CF_7_TC
	bnez	t1, Conf7KL2		/* Any L3 disabled if set */
	li	s8, 0

	li	s8, 1024 * 1024 * 2
#if 0
	li	t0, CF_7_TS		/* Use when cache size is in cfg reg */
	and	t1, t3, t0
	beq	t1, t0, Conf7KL2
	srl	t1, CF_7_TS_AL

	li	s8, 5024288		/* 512k */
	sll	s8, t1
#endif

Conf7KL2:
	and	t1, t3, CF_7_SC
	bnez	t1, Conf7KEnd
	li	s7, 0

	li	s7, 262144		/* Size of L2 cache */

#endif
	li      s7,0
	li      s8,0

Conf7KEnd:

	TTYDBG("Disable cache exceptions...\r\n");

	mfc0	t0, COP_0_STATUS_REG
	and	t1, t0, SR_BOOT_EXC_VEC
	or	t1, SR_DIAG_DE
	mtc0	t1, COP_0_STATUS_REG

	mtc0	zero, COP_0_TAG_LO
	mtc0	zero, COP_0_TAG_HI
	mtc0	zero, COP_0_ECC

	and	t2, t3, ~(CF_7_SE|CF_7_TE)
	mtc0	t2, COP_0_CONFIG		/* Disable L2 and L3 */
	NOP8

/*
 *  Do L1 instruction cache.
 */

	TTYDBG("Init L1 instruction cache...\r\n")

	la	a0, CACHED_MEMORY_ADDR
	addu	a1, a0, s3			/* End = size of I cache */

1:
	addu	a0, s4				/* Step by line size */
	cache	IndexStoreTagI, -4(a0)
	nop
	cache	FillI, -4(a0)
	nop
	bne	a0, a1, 1b
	cache	IndexStoreTagI, -4(a0)

/*
 *  Do L1 data cache.
 */

	TTYDBG("Init L1 data cache...\r\n")

	la	a0, CACHED_MEMORY_ADDR
	add	a1, a0, s5			/* End = size of D cache */

1:
	addu	a0, s6				/* Step by line size */
	bne	a0, a1, 1b
	cache	IndexStoreTagD, -4(a0)

	la	a0, CACHED_MEMORY_ADDR
	add	a1, a0, s5			/* End = size of D cache */

1:
	addu	a0, s6				/* Step by line size */
	bne	a0, a1, 1b
	lw	zero, -4(a0)

	la	a0, CACHED_MEMORY_ADDR
	add	a1, a0, s5			/* End = size of D cache */

1:
	addu	a0, s6				/* Step by line size */
	bne	a0, a1, 1b
	cache	IndexStoreTagD, -4(a0)

	beqz	s7, no_L2_cache
	nop

/*
 *  Do L2 cache
 */

	TTYDBG("Init L2 unified cache...\r\n")

	or	t3, CF_7_SE			/* Enable secondary cache */
	mtc0	t3, COP_0_CONFIG
	NOP8

	la	a0, CACHED_MEMORY_ADDR
	add	a1, a0, s7			/* End = size of L2 cache */

1:
	addu	a0, 32				/* Step by line size */
	bne	a0, a1, 1b
	cache	IndexStoreTagS, -4(a0)

	sync

	la	a0, CACHED_MEMORY_ADDR
	add	a1, a0, s7			/* End = size of L2 cache */

1:
	addu	a0, 32				/* Step by line size */
	bne	a0, a1, 1b
	lw	zero, -4(a0)

	sync

	la	a0, CACHED_MEMORY_ADDR
	add	a1, a0, s7			/* End = size of L2 cache */

1:
	addu	a0, 32				/* Step by line size */
	bne	a0, a1, 1b
	cache	IndexStoreTagS, -4(a0)

	sync

no_L2_cache:

/*
 *  Do any L3 cache
 */

	beqz	s8, no_L3_cache			/* Any L3 size? */
	nop

	TTYDBG("Init L3 unified cache...\r\n")

	or	t3, CF_7_TE			/* Enable tertiary cache */
	mtc0	t3, COP_0_CONFIG
	NOP8

	mtc0	zero, COP_0_TAG_HI
	mtc0	zero, COP_0_TAG_LO

	la	a0, CACHED_MEMORY_ADDR
	addu	a1, a0, s8			/* Compute size of L3 */

1:
	cache	IndexStoreTagT, 0(a0)
	addu	a0, 32
	bne	a0, a1, 1b
	nop

	lw	a0, CPU_CONFIG(s2)		/* Set GT64240 for L3 cache */
	li	a1, HTOLE32(0x00004000)	
	or	a0, a0, a1
	sw	a0, CPU_CONFIG(s2)

no_L3_cache:

	mtc0	t0, COP_0_STATUS_REG		/* Restore status reg */
	mtc0	t3, COP_0_CONFIG		/* Restore cache config */
	NOP8

cache_done:

#ifdef DEBUG_LOCORE
	TTYDBG("Init caches done, cfg = ")
	mfc0	a0, COP_0_CONFIG
	bal	hexserial
	nop
	TTYDBG("\r\n")
#endif
#if 0 
	TTYDBG("Testing memory...\r\n")

	li	t7, 10
tmem:
	li	t0, 0xa0000000+1*1024*1024
	li	t1, 0xa0000000
	li	t2, 0xffffffff
1:
	sw	t2, 0(t1)
	lw	t3, 0(t1)
	bne	t3, t2, 1f
	nop
	not	t2
	sw	t2, 0(t1)
	lw	t3, 0(t1)
	bne	t3, t2, 1f
	nop
	not t2
	addu	t2, 1
	addu	t1, 4
	beq	t1, t0, 2f
	nop
	and	t4, t1, 0x000fffff
	bnez	t4, skipdot
	li	a0, '.'
	bal	tgt_putchar
	nop
skipdot:
	b	1b
	nop
1:
	TTYDBG("Memory test failed at ");
	move	a0,	t1
	bal	hexserial
	nop
	TTYDBG("\r\nWrite=");
	move	a0, t2
	bal	hexserial
	nop
	TTYDBG("\r\nRead=");
	move	a0, t3
	bal	hexserial
	nop
1:
	b	1b
	nop
2:
	TTYDBG("Testing ok...\r\n");
	sub	t7,1
	beqz	t7, 1f
	nop
	b	tmem
	nop
1:	
	b	1b
	nop
#endif



/*
 *  At this point all memory controller setup should have been done
 *  and we should be able to function 'normally' and C code can be
 *  used freely from this point.
 */
	TTYDBG("Copy PMON to execute location...\r\n")