start.s

国产CPU－龙芯（loongson)BIOS源代码

	bal	hexserial
	lw	a0, SCS_1_HIGH_DECODE_ADDRESS(s2)

	TTYDBG("\r\nSCS_2=");
	bal	hexserial
	lw	a0, SCS_2_LOW_DECODE_ADDRESS(s2)
	TTYDBG("~");
	bal	hexserial
	lw	a0, SCS_2_HIGH_DECODE_ADDRESS(s2)

	TTYDBG("\r\nSCS_3=");
	bal	hexserial
	lw	a0, SCS_3_LOW_DECODE_ADDRESS(s2)
	TTYDBG("~");
	bal	hexserial
	lw	a0, SCS_3_HIGH_DECODE_ADDRESS(s2)
	
	TTYDBG("\r\n");

/*
 *  Clear out 2Mb of memory (maximum cache size)
 */

	TTYDBG("Clearing cache size memory...\r\n");

	la	t0, UNCACHED_MEMORY_ADDR
	addu	t1, t0, 2*1024*1024
1:
	addu	t0, 8
	bne	t1, t0, 1b
	sd	zero, -8(t0)

	TTYDBG("Init SDRAM Done!\r\n");
	b	do_caches
	nop

in_ram:
	PRINTSTR("RAM loaded\r\n");
/*
 *  Reset and initialize caches to a known state.
 */
#define IndexStoreTagI	0x08
#define IndexStoreTagD	0x09
#define IndexStoreTagS	0x0b
#define IndexStoreTagT	0x0a
#define FillI		0x14

/*
 *  RM7000 config register bits.
 */
#define CF_7_SE         (1 << 3)        /* Secondary cache enable */
#define CF_7_SC         (1 << 31)       /* Secondary cache not present */
#define CF_7_TE         (1 << 12)       /* Tertiary cache enable */
#define CF_7_TC         (1 << 17)       /* Tertiary cache not present */
#define CF_7_TS         (3 << 20)       /* Tertiary cache size */
#define CF_7_TS_AL      20              /* Shift to align */
#define NOP8 nop;nop;nop;nop;nop;nop;nop;nop
do_caches:
	TTYDBG("Sizing caches...\r\n");

	mfc0	t3, COP_0_CONFIG	/* t3 = original config */
	and	t3, 0xffffeff0		/* Make sure coherency is OK */

	and	t3, ~(CF_7_TE|CF_7_SE|CF_7_TC|CF_7_SC)  /* disable L2/L3 cache */
	mtc0    t3, COP_0_CONFIG

	li	t2, 4096

	srl	t1, t3, 9
	and	t1, 3
	sllv	s3, t2, t1		/* s3 = I cache size */

	and	t1, t3, 0x20
	srl	t1, t1, 1
	addu	s4, t1, 16		/* s4 = I cache line size */

	srl	t1, t3, 6
	and	t1, 3
	sllv	s5, t2, t1		/* s5 = D cache size */

	and	t1, t3, 0x10
	addu	s6, t1, 16		/* s6 = D cache line size */
	TTYDBG("Init caches...\r\n")

	li	s7, 0                   /* no L2 cache */
	li	s8, 0                   /* no L3 cache */

	mfc0    a0, COP_0_PRID
	li      a1, 0x6300
	bne     a0,a1,1f
	nop
	TTYDBG("godson2 caches found\r\n")
        bal     godson2_cache_init
        nop
	b	cache_done
	nop
1:

#if 0

	and	t1, t3, CF_7_TC
	bnez	t1, Conf7KL2		/* Any L3 disabled if set */
	li	s8, 0

	li	s8, 1024 * 1024 * 2
#if 0
	li	t0, CF_7_TS		/* Use when cache size is in cfg reg */
	and	t1, t3, t0
	beq	t1, t0, Conf7KL2
	srl	t1, CF_7_TS_AL

	li	s8, 5024288		/* 512k */
	sll	s8, t1
#endif

Conf7KL2:
	and	t1, t3, CF_7_SC
	bnez	t1, Conf7KEnd
	li	s7, 0

	li	s7, 262144		/* Size of L2 cache */

#endif
	li      s7,0
	li      s8,0

Conf7KEnd:

	TTYDBG("Disable cache exceptions...\r\n");

	mfc0	t0, COP_0_STATUS_REG
	and	t1, t0, SR_BOOT_EXC_VEC
	or	t1, SR_DIAG_DE
	mtc0	t1, COP_0_STATUS_REG

	mtc0	zero, COP_0_TAG_LO
	mtc0	zero, COP_0_TAG_HI
	mtc0	zero, COP_0_ECC

	and	t2, t3, ~(CF_7_SE|CF_7_TE)
	mtc0	t2, COP_0_CONFIG		/* Disable L2 and L3 */
	NOP8

/*
 *  Do L1 instruction cache.
 */

	TTYDBG("Init L1 instruction cache...\r\n")

	la	a0, CACHED_MEMORY_ADDR
	addu	a1, a0, s3			/* End = size of I cache */

1:
	addu	a0, s4				/* Step by line size */
	cache	IndexStoreTagI, -4(a0)
	nop
	cache	FillI, -4(a0)
	nop
	bne	a0, a1, 1b
	cache	IndexStoreTagI, -4(a0)

/*
 *  Do L1 data cache.
 */

	TTYDBG("Init L1 data cache...\r\n")

	la	a0, CACHED_MEMORY_ADDR
	add	a1, a0, s5			/* End = size of D cache */

1:
	addu	a0, s6				/* Step by line size */
	bne	a0, a1, 1b
	cache	IndexStoreTagD, -4(a0)

	la	a0, CACHED_MEMORY_ADDR
	add	a1, a0, s5			/* End = size of D cache */

1:
	addu	a0, s6				/* Step by line size */
	bne	a0, a1, 1b
	lw	zero, -4(a0)

	la	a0, CACHED_MEMORY_ADDR
	add	a1, a0, s5			/* End = size of D cache */

1:
	addu	a0, s6				/* Step by line size */
	bne	a0, a1, 1b
	cache	IndexStoreTagD, -4(a0)

	beqz	s7, no_L2_cache
	nop

/*
 *  Do L2 cache
 */

	TTYDBG("Init L2 unified cache...\r\n")

	or	t3, CF_7_SE			/* Enable secondary cache */
	mtc0	t3, COP_0_CONFIG
	NOP8

	la	a0, CACHED_MEMORY_ADDR
	add	a1, a0, s7			/* End = size of L2 cache */

1:
	addu	a0, 32				/* Step by line size */
	bne	a0, a1, 1b
	cache	IndexStoreTagS, -4(a0)

	sync

	la	a0, CACHED_MEMORY_ADDR
	add	a1, a0, s7			/* End = size of L2 cache */

1:
	addu	a0, 32				/* Step by line size */
	bne	a0, a1, 1b
	lw	zero, -4(a0)

	sync

	la	a0, CACHED_MEMORY_ADDR
	add	a1, a0, s7			/* End = size of L2 cache */

1:
	addu	a0, 32				/* Step by line size */
	bne	a0, a1, 1b
	cache	IndexStoreTagS, -4(a0)

	sync

no_L2_cache:

/*
 *  Do any L3 cache
 */

	beqz	s8, no_L3_cache			/* Any L3 size? */
	nop

	TTYDBG("Init L3 unified cache...\r\n")

	or	t3, CF_7_TE			/* Enable tertiary cache */
	mtc0	t3, COP_0_CONFIG
	NOP8

	mtc0	zero, COP_0_TAG_HI
	mtc0	zero, COP_0_TAG_LO

	la	a0, CACHED_MEMORY_ADDR
	addu	a1, a0, s8			/* Compute size of L3 */

1:
	cache	IndexStoreTagT, 0(a0)
	addu	a0, 32
	bne	a0, a1, 1b
	nop

	lw	a0, CPU_CONFIG(s2)		/* Set GT64240 for L3 cache */
	li	a1, HTOLE32(0x00004000)	
	or	a0, a0, a1
	sw	a0, CPU_CONFIG(s2)

no_L3_cache:

	mtc0	t0, COP_0_STATUS_REG		/* Restore status reg */
	mtc0	t3, COP_0_CONFIG		/* Restore cache config */
	NOP8

cache_done:

#ifdef DEBUG_LOCORE
	TTYDBG("Init caches done, cfg = ")
	mfc0	a0, COP_0_CONFIG
	bal	hexserial
	nop
	TTYDBG("\r\n")
#endif
#if 0 
	TTYDBG("Testing memory...\r\n")

	li	t7, 10
tmem:
	li	t0, 0xa0000000+1*1024*1024
	li	t1, 0xa0000000
	li	t2, 0xffffffff
1:
	sw	t2, 0(t1)
	lw	t3, 0(t1)
	bne	t3, t2, 1f
	nop
	not	t2
	sw	t2, 0(t1)
	lw	t3, 0(t1)
	bne	t3, t2, 1f
	nop
	not t2
	addu	t2, 1
	addu	t1, 4
	beq	t1, t0, 2f
	nop
	and	t4, t1, 0x000fffff
	bnez	t4, skipdot
	li	a0, '.'
	bal	tgt_putchar
	nop
skipdot:
	b	1b
	nop
1:
	TTYDBG("Memory test failed at ");
	move	a0,	t1
	bal	hexserial
	nop
	TTYDBG("\r\nWrite=");
	move	a0, t2
	bal	hexserial
	nop
	TTYDBG("\r\nRead=");
	move	a0, t3
	bal	hexserial
	nop
1:
	b	1b
	nop
2:
	TTYDBG("Testing ok...\r\n");
	sub	t7,1
	beqz	t7, 1f
	nop
	b	tmem
	nop
1:	
	b	1b
	nop
#endif



/*
 *  At this point all memory controller setup should have been done
 *  and we should be able to function 'normally' and C code can be
 *  used freely from this point.
 */
	TTYDBG("Copy PMON to execute location...\r\n")
#ifdef DEBUG_LOCORE
	TTYDBG("start = ")
	la	a0, start
	bal	hexserial
	nop
	TTYDBG("\r\ns0 = ")
	move	a0, s0
	bal	hexserial
	nop
	TTYDBG("\r\n")
#endif
	la	a0, start
	li	a1, 0xbfc00000
	la	a2, _edata
	subu	t1, a2, a0
	srl t1, t1, 2

	/* copy text section */
	li	t0, 0
1:	lw	v0, 0(a1)
	nop
	sw	v0, 0(a0)
	addu	a0, 4
	bne a2, a0, 1b
	addu	a1, 4
	
	/* Clear BSS */
	la	a0, _edata
	la	a2, _end
2:	sw	zero, 0(a0)
	bne a2, a0, 2b
	addu	a0, 4
#if 0
	la	a1, start	/* RAM start address */
	la	v0, copytoram
	addu	v0, s0		/* Compute ROM address of 'copytoram' */
	jal	v0
	add	a0, a1, s0	/* ROM start address */

	beqz	v0, 1f
	nop

	move	s3, v0
	PRINTSTR("\r\nPANIC! Copy to memory failed at 0x")
	move	a0, s3
	bal	hexserial
	nop
	PRINTSTR(".\r\n")
	b	stuck
	nop
#endif

1:
	TTYDBG("Copy PMON to execute location done.\r\n")

	move	a3,s1	
	
#ifdef SKIPDIMM
	li	a3,	256
#endif

	la	a0, start
	la	a2, _edata
	subu	a2, a2, a0
	srl	a1, a1, 2
	la	v0, decompress_pmon
	jalr	v0
	nop

stuck:
#ifdef DEBUG_LOCORE
	TTYDBG("Dumping GT64240 setup.\r\n")
	TTYDBG("offset----data------------------------.\r\n")
	li	s3, 0
1:
	move	a0, s3
	bal	hexserial
	nop
	TTYDBG(": ")
2:
	add	a0, s3, s2
	lw	a0, 0(a0)
	bal	hexserial
	addiu	s3, 4
	TTYDBG(" ")
	li	a0, 0xfff
	and	a0, s3
	beqz	a0, 3f
	li	a0, 0x01f
	and	a0, s3
	bnez	a0, 2b
	TTYDBG("\r\n")
	b	1b
	nop
3:
	b	3b
	nop

#else
	b	stuck
	nop
#endif

/*
 *  Clear the TLB. Normally called from start.S.
 */
LEAF(CPU_TLBClear)
	li	a3, 0			# First TLB index.

	li	a2, PG_SIZE_4K
	dmtc0   a2, COP_0_TLB_PG_MASK   # Whatever...

1:
	dmtc0   zero, COP_0_TLB_HI	# Clear entry high.
	dmtc0   zero, COP_0_TLB_LO0	# Clear entry low0.
	dmtc0   zero, COP_0_TLB_LO1	# Clear entry low1.

	mtc0    a3, COP_0_TLB_INDEX	# Set the index.
	addiu	a3, 1
	li	a2, 64
	nop
	nop
	tlbwi				# Write the TLB

	bne	a3, a2, 1b
	nop

	jr	ra
	nop
END(CPU_TLBClear)

/*
 *  Set up the TLB. Normally called from start.S.
 */
LEAF(CPU_TLBInit)
	li	a3, 0			# First TLB index.

	li	a2, PG_SIZE_16M
	dmtc0   a2, COP_0_TLB_PG_MASK   # All pages are 16Mb.

1:
	and	a2, a0, PG_SVPN
	dmtc0   a2, COP_0_TLB_HI	# Set up entry high.

	move	a2, a0
	srl	a2, a0, PG_SHIFT 
	and	a2, a2, PG_FRAME
	ori	a2, PG_IOPAGE
	dmtc0   a2, COP_0_TLB_LO0	# Set up entry low0.
	addu	a2, (0x01000000 >> PG_SHIFT)
	dmtc0   a2, COP_0_TLB_LO1	# Set up entry low1.

	mtc0    a3, COP_0_TLB_INDEX	# Set the index.
	addiu	a3, 1
	li	a2, 0x02000000
	subu	a1, a2
	nop
	tlbwi				# Write the TLB

	bgtz	a1, 1b
	addu	a0, a2			# Step address 32Mb.

	jr	ra
	nop
END(CPU_TLBInit)

/*
 *  Set DEVPAR for device bus timing.
 */

	.globl	tgt_setpar125mhz
tgt_setpar125mhz:
	move	a0, ra		/* Don't put in delay slot! */
	bal	do_table	/* Load address to init table */
	nop

	/* Device CS0 - PLD */
        GTINIT(DEVICE_BANK0PARAMETERS, \
				GT_DEVPAR_TurnOff(2) |		\
				GT_DEVPAR_AccToFirst(8) |	\
				GT_DEVPAR_AccToNext(8)	|	\
				GT_DEVPAR_ALEtoWr(3) |		\
				GT_DEVPAR_WrActive(3) |		\
				GT_DEVPAR_WrHigh(5) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_Reserved)

	/* Device CS1 - RTC */
        GTINIT(DEVICE_BANK1PARAMETERS, \
				GT_DEVPAR_TurnOff(2) |		\
				GT_DEVPAR_AccToFirst(13) |	\
				GT_DEVPAR_AccToNext(13)	|	\
				GT_DEVPAR_ALEtoWr(5) |		\
				GT_DEVPAR_WrActive(7) |		\
				GT_DEVPAR_WrHigh(5) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_Reserved)

	/* Device CS2 - UART */
        GTINIT(DEVICE_BANK2PARAMETERS, \
				GT_DEVPAR_TurnOff(3) |		\
				GT_DEVPAR_AccToFirst(15) |	\
				GT_DEVPAR_AccToNext(15)	|	\
				GT_DEVPAR_ALEtoWr(5) |		\
				GT_DEVPAR_WrActive(8) |		\
				GT_DEVPAR_WrHigh(5) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_Reserved)
				
	/* end mark */
	.word	0, 0

	.globl	tgt_setpar100mhz
tgt_setpar100mhz:
	move	a0, ra		/* Don't put in delay slot! */
	bal	do_table	/* Load address to init table */
	nop

	/* Device CS0 - PLD */
        GTINIT(DEVICE_BANK0PARAMETERS, \
				GT_DEVPAR_TurnOff(3) |		\
				GT_DEVPAR_AccToFirst(6) |	\
				GT_DEVPAR_AccToNext(6)	|	\
				GT_DEVPAR_ALEtoWr(3) |		\
				GT_DEVPAR_WrActive(3) |		\
				GT_DEVPAR_WrHigh(5) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_Reserved)

	/* Device CS1 - NVRAM */
        GTINIT(DEVICE_BANK1PARAMETERS, \
				GT_DEVPAR_TurnOff(3) |		\
				GT_DEVPAR_AccToFirst(10) |	\
				GT_DEVPAR_AccToNext(10)	|	\
				GT_DEVPAR_ALEtoWr(5) |		\
				GT_DEVPAR_WrActive(6) |		\
				GT_DEVPAR_WrHigh(5) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_Reserved)

	/* Device CS2 - UART */
        GTINIT(DEVICE_BANK2PARAMETERS, \
				GT_DEVPAR_TurnOff(4) |		\
				GT_DEVPAR_AccToFirst(11) |	\
				GT_DEVPAR_AccToNext(11)	|	\
				GT_DEVPAR_ALEtoWr(5) |		\
				GT_DEVPAR_WrActive(6) |		\
				GT_DEVPAR_WrHigh(5) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_Reserved)
	/* end mark */
	.word	0, 0

1:
	sw	v1, 0(v0)
do_table:
	lw	v0, 0(ra)		/* Address */
	lw	v1, 4(ra)		/* Data */
	bnez	v0, 1b
	addiu	ra, 8

	jr	a0
	nop


/*
 * Simple character printing routine used before full initialization
 */

LEAF(stringserial)
	move	a2, ra
	addu	a1, a0, s0
	lbu	a0, 0(a1)
1:
	beqz	a0, 2f
	nop
	bal	tgt_putchar
	addiu	a1, 1
	b	1b
	lbu	a0, 0(a1)

2:
	j	a2
	nop
END(stringserial)

LEAF(stringserial_zsh)
	move	a2, ra
	lbu	a0, 0(a1)
1:
	beqz	a0, 2f
	nop
	bal	tgt_putchar
	addiu	a1, 1
	b	1b
	lbu	a0, 0(a1)

2:
	j	a2
	nop
END(stringserial_zsh)

LEAF(hexserial_zfx)
	move	a2, ra
	move	a1, a0
	li	a3, 7
1:
	rol	a0, a1, 4
	move	a1, a0
	and	a0, 0xf
	la	v0, hexchar
	addu	v0, a0
#	bal	tgt_putchar
#	lbu	a0, 0(v0)

	bnez	a3, 1b
	addu	a3, -1
#	bal	tgt_putchar
#	li	a0, 0xd
#	bal	tgt_putchar
	li	a0, 0xa

	j	a2
	nop
END(hexserial_zfx)

LEAF(hexserial)
	move	a2, ra
	move	a1, a0
	li	a3, 7
1:
	rol	a0, a1, 4
	move	a1, a0
	and	a0, 0xf
	la	v0, hexchar
	addu	v0, s0
	addu	v0, a0
	bal	tgt_putchar
	lbu	a0, 0(v0)

	bnez	a3, 1b
	addu	a3, -1

	j	a2
	nop
END(hexserial)
	

#if 0
LEAF(tgt_putchar)
	move   t8,ra
	bal     1f
	nop
1:
	addu   ra,ra,16
	or     ra,ra,0x20000000
	jr     ra
        nop

	la	v0, COM1_BASE_ADDR
1:
	lbu	v1, NSREG(NS16550_LSR)(v0)
	and	v1, LSR_TXRDY
	beqz	v1, 1b
	nop

	sb	a0, NSREG(NS16550_DATA)(v0)

        move    ra,t8
  
	j	ra
	nop	
END(tgt_putchar)
#endif

LEAF(tgt_putchar)
	la	v0, COM1_BASE_ADDR
1:
	lbu	v1, NSREG(NS16550_LSR)(v0)
	and	v1, LSR_TXRDY
	beqz	v1, 1b
	nop

	sb	a0, NSREG(NS16550_DATA)(v0)

	j	ra
	nop	
END(tgt_putchar)

/* baud rate definitions, matching include/termios.h */
#define B0      0
#define B50     50      
#define B75     75
#define B110    110
#define B134    134
#define B150    150
#define B200    200
#define B300    300
#define B600    600
#define B1200   1200
#define B1800   1800
#define B2400   2400
#define B4800   4800
#define B9600   9600
#define B19200  19200
#define B38400  38400
#define B57600  57600
#define B115200 115200

LEAF(initserial)
	la	v0, COM1_BASE_ADDR
1:
	li	v1, FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4
	sb	v1, NSREG(NS16550_FIFO)(v0)
	li	v1, CFCR_DLAB
	sb	v1, NSREG(NS16550_CFCR)(v0)
 	li	v1, NS16550HZ/(16*CONS_BAUD)
	sb	v1, NSREG(NS16550_DATA)(v0)
	srl	v1, 8
	sb	v1, NSREG(NS16550_IER)(v0)
	li	v1, CFCR_8BITS
	sb	v1, NSREG(NS16550_CFCR)(v0)
#if 0
	li	v1, MCR_DTR|MCR_RTS
#endif
	sb	v1, NSREG(NS16550_MCR)(v0)
	li	v1, 0x0
	sb	v1, NSREG(NS16550_IER)(v0)
#if 0
	move	v1, v0
	la	v0, COM2_BASE_ADDR
	bne	v0, v1, 1b
	nop
#endif
	j	ra
	nop
END(initserial)

__main:
	j	ra
	nop


	.rdata
transmit_pat_msg:
	.asciz	"\r\nInvalid transmit pattern.  Must be DDDD or DDxDDx\r\n"
v200_msg:
	.asciz	"\r\nPANIC! Unexpected TLB refill exception!\r\n"
v280_msg:
	.asciz	"\r\nPANIC! Unexpected XTLB refill exception!\r\n"
v380_msg:
	.asciz	"\r\nPANIC! Unexpected General exception!\r\n"
v400_msg:
	.asciz	"\r\nPANIC! Unexpected Interrupt exception!\r\n"
hexchar:
	.ascii	"0123456789abcdef"

	.text
	.align	2


/*
 *   I2C Functions used in early startup code to get SPD info from