start.s

国产CPU－龙芯（loongson)BIOS源代码

/*	$Id: start.S,v 1.2 2003/11/11 02:19:43 wlin Exp $ */

/*
 * Copyright (c) 2001 Opsycon AB  (www.opsycon.se)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Opsycon AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef _KERNEL
#define _KERNEL
#endif

#include <asm.h>
#include <regnum.h>
#include <cpu.h>
#include <pte.h>

#include "target/ev64240.h"

#include "pmon/dev/ns16550.h"
#include "pmon/dev/gt64240reg.h"

#ifdef GODSONEV2A
#	define SKIPDIMM
#	define SDRAM_MODE_FIX
#else
#	undef SKIPDIMM
#	undef SDRAM_MODE_FIX
#endif

#undef RUN_SDRAM_FAST

#define DEBUG_LOCORE 1
#ifdef DEBUG_LOCORE
#define	TTYDBG(x) \
	.rdata;98: .asciz x; .text; la a0, 98b; bal stringserial; nop
#else
#define TTYDBG(x)
#endif

#define	PRINTSTR(x) \
	.rdata;98: .asciz x; .text; la a0, 98b; bal stringserial; nop

#define GTINIT(offset, value) \
	.word	GT_BASE_ADDR+(offset), HTOLE32(value)

/*
 *   Register usage:
 *
 *	s0	link versus load offset, used to relocate absolute adresses.
 *	s1	free
 *	s2	base address to Galileo chip.
 *	s3	L1 I cache size.
 *	s4	L1 I cache line size.
 *	s5	L1 D cache size.
 *	s6	L1 D cache line size.
 *	s7	L2 Cache size.
 *	s8	L3 Cache size.
 */


	.set	noreorder

	.globl	_start
	.globl	start
	.globl	__main
_start:
start:
	.globl	stack
stack = start - 0x4000		/* Place PMON stack below PMON start in RAM */

/* NOTE!! Not more that 16 instructions here!!! Right now it's FULL! */
	mtc0	zero, COP_0_STATUS_REG

	li	t0, SR_BOOT_EXC_VEC	/* Exception to Boostrap Location */
	mtc0	t0, COP_0_STATUS_REG

	lui     a0,0x3000
	li      a1,SR_BOOT_EXC_VEC
	or      a0,a0,a1
	mtc0    a0, COP_0_STATUS_REG

	mtc0	zero, COP_0_CAUSE_REG
	la	sp, stack
	la	gp, _gp

	bal	uncached		/* Switch to uncached address space */
	nop

	bal	locate			/* Get current execute address */
	nop

uncached:
	or	ra, UNCACHED_MEMORY_ADDR
	j	ra
	nop

/*
 *  Reboot vector usable from outside pmon.
 */
	.align	8
ext_map_and_reboot:
	bal	CPU_TLBClear
	nop

	li	a0, 0xc0000000
	li	a1, 0x40000000
	bal	CPU_TLBInit
	nop
	la	v0, tgt_reboot
	la	v1, start
	subu	v0, v1
	lui	v1, 0xffc0
	addu	v0, v1
	jr	v0
	nop

/*
 *  Exception vectors here for rom, before we are up and running. Catch
 *  whatever comes up before we have a fully fledged exception handler.
 */
	.align	9			/* bfc00200 */
	la	a0, v200_msg
	bal	stringserial
	nop
	b	exc_common

	.align	7			/* bfc00280 */
	la	a0, v280_msg
	bal	stringserial
	nop
	b	exc_common

/* Cache error */
	.align	8			/* bfc00300 */
	PRINTSTR("\r\nPANIC! Unexpected Cache Error exception! ")
	mfc0	a0, COP_0_CACHE_ERR
	bal	hexserial
	nop
	b	exc_common

/* General exception */
	.align	7			/* bfc00380 */

/* make keg0 uncached to make sure prints works! */
#if 0
        mfc0    a0,COP_0_CONFIG
        and    a0,a0,0xfffffff8
        or     a0,a0,0x2
	mtc0   a0,COP_0_CONFIG
#endif
#if 1
	lui a1, 0xa040
        nop
	mfc0 a0, COP_0_EXC_PC
        nop
	sw a0, (a1)
        nop
	mfc0 a0, COP_0_CAUSE_REG
        nop
	sw a0, (a1)
        nop
	dmfc0 a0, $8
        nop
	dsrl a0,a0,32
        nop
	sw a0, (a1)
        nop
	mfc0 a0, $8
        nop
	sw a0, (a1)
        nop

	mfc0 a0, COP_0_EXC_PC
	nop
	lw a0, (a0)
	nop
	sw a0, (a1)
	nop

#endif

	la	a0, v380_msg
	bal	stringserial
	nop
	b	exc_common

	.align	8			/* bfc00400 */
	la	a0, v400_msg
	bal	stringserial
	nop

exc_common:
	PRINTSTR("\r\nERRORPC=")
	mfc0	a0, COP_0_ERROR_PC
	bal	hexserial
	nop
	PRINTSTR("\r\nEPC=")
	mfc0	a0, COP_0_EXC_PC
	bal	hexserial
	nop
	PRINTSTR("\r\n(EPC)=")
	mfc0	a0, COP_0_EXC_PC
	lw	a0, (a0)
	bal	hexserial
	nop

	PRINTSTR("\r\nSTATUS=")
	mfc0	a0, COP_0_STATUS_REG
	bal	hexserial
	nop
	PRINTSTR("\r\nCAUSE=")
	mfc0	a0, COP_0_CAUSE_REG
	bal	hexserial
	nop
	PRINTSTR("\r\nBADVADDR=")
	dmfc0	a0, $8
        dsrl  a0,a0,32
	bal	hexserial
        nop
	dmfc0	a0, $8
	bal	hexserial
	nop

	PRINTSTR("\r\nDERR0=")
	cfc0	a0, COP_0_DERR_0
	bal	hexserial
	nop
	PRINTSTR("\r\nDERR1=")
	cfc0	a0, COP_0_DERR_1
	bal	hexserial
	nop
	
	1:	 b  1b
        nop
	 
//	b	ext_map_and_reboot
	nop


/*
 *  We get here from executing a bal to get the PC value of the current execute
 *  location into ra. Check to see if we run from ROM or if this is ramloaded.
 */
	
locate:
	bal init_regs
	nop


	la	s0, start		/* RA set from BAL above! */
	subu	s0, ra, s0		/* s0 is now load vs. link offset */
	and	s0, 0xffff0000		/* Mask off lower bits */

/*
 *  Clean out and initialize the TLB
 */
	bal	CPU_TLBClear
	nop

	li	a0, 0xc0000000
	li	a1, 0x40000000
	bal	CPU_TLBInit
	nop

/*
 *  Turn off all high decoders to avoid address conflicts.
 */
	la	s2, GT_BASE_ADDR_DEFAULT
	li	t0, HTOLE32(0x00000fff)
	sw	t0, PCI_0I_O_LOW_DECODE_ADDRESS(s2)
	sw	t0, PCI_0MEMORY0_LOW_DECODE_ADDRESS(s2)
	sw	t0, PCI_0MEMORY1_LOW_DECODE_ADDRESS(s2)
	sw	t0, PCI_0MEMORY2_LOW_DECODE_ADDRESS(s2)
	sw	t0, PCI_0MEMORY3_LOW_DECODE_ADDRESS(s2)
	sw	zero, PCI_0I_O_HIGH_DECODE_ADDRESS(s2)
	sw	zero, PCI_0MEMORY0_HIGH_DECODE_ADDRESS(s2)
	sw	zero, PCI_0MEMORY1_HIGH_DECODE_ADDRESS(s2)
	sw	zero, PCI_0MEMORY2_HIGH_DECODE_ADDRESS(s2)
	sw	zero, PCI_0MEMORY3_HIGH_DECODE_ADDRESS(s2)
	sw	t0, PCI_1I_O_LOW_DECODE_ADDRESS(s2)
	sw	t0, PCI_1MEMORY0_LOW_DECODE_ADDRESS(s2)
	sw	t0, PCI_1MEMORY1_LOW_DECODE_ADDRESS(s2)
	sw	t0, PCI_1MEMORY2_LOW_DECODE_ADDRESS(s2)
	sw	t0, PCI_1MEMORY3_LOW_DECODE_ADDRESS(s2)
	sw	zero, PCI_1I_O_HIGH_DECODE_ADDRESS(s2)
	sw	zero, PCI_1MEMORY0_HIGH_DECODE_ADDRESS(s2)
	sw	zero, PCI_1MEMORY1_HIGH_DECODE_ADDRESS(s2)
	sw	zero, PCI_1MEMORY2_HIGH_DECODE_ADDRESS(s2)
	sw	zero, PCI_1MEMORY3_HIGH_DECODE_ADDRESS(s2)
#if 1
	li	t0, HTOLE32(0x00000101)
	sw	t0, PCI_1I_O_LOW_DECODE_ADDRESS(s2)
	li	t0, HTOLE32(0x00000101)
	sw	t0, PCI_1I_O_HIGH_DECODE_ADDRESS(s2)
	sw	zero, PCI_1I_O_ADDRESS_REMAP(s2)

	li	t0, HTOLE32(0x80000004)
	sw	t0, PCI_1CONFIGURATION_ADDRESS(s2)
	lw	t1, PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER(s2)
	ori	t1, 0x02|0x04
	sw	t0, PCI_1CONFIGURATION_ADDRESS(s2)
	sw	t1, PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER(s2)

	lw	t0, PCI_0ARBITER_CONTROL(s2)
	or	t0, t0, HTOLE32(0x80000000)
	sw	t0, PCI_0ARBITER_CONTROL(s2)
	lw	t0, PCI_1ARBITER_CONTROL(s2)
	or	t0, t0, HTOLE32(0x80000000)
	sw	t0, PCI_1ARBITER_CONTROL(s2)
#endif
/*
 *  Relocate the Galileo to HIGH memory.
 */
	li	t0, HTOLE32((UNCACHED_TO_PHYS(GT_BASE_ADDR) >> 20) | 0x01000000)
	sw	t0, INTERNAL_SPACE_DECODE(s2)

	li	t0, 0x100		/* Need a small delay here */
1:
	bnez	t0, 1b
	addiu	t0, -1

	la	s2, GT_BASE_ADDR	/* From now this is the GT base */
//	bal	tgt_setpar125mhz	/* Set bus timing for 125MHz */
	bal	tgt_setpar100mhz	/* Set bus timing for 125MHz */
	nop				/* Changed later if 100Mhz bus */

	lw	t0, CPU_CONFIG(s2)	/* Turn off  automatic retries */
	li	t1, HTOLE32(0x00020000)	
	or	t0, t0, t1
	sw	t0, CPU_CONFIG(s2)

/*
 *  Set up I/O decoders to point correctly.
 */
	bal	2f	/* Load address to init table */
	nop

	GTINIT(CS_0_LOW_DECODE_ADDRESS, UNCACHED_TO_PHYS(SRAM_BASE) >> 20)
	GTINIT(CS_0_HIGH_DECODE_ADDRESS, (UNCACHED_TO_PHYS(SRAM_BASE) + SRAM_SIZE - 1) >> 20)
	GTINIT(CS_1_LOW_DECODE_ADDRESS, UNCACHED_TO_PHYS(RTC_BASE) >> 20)
	GTINIT(CS_1_HIGH_DECODE_ADDRESS, (UNCACHED_TO_PHYS(RTC_BASE) + RTC_SIZE - 1) >> 20)
	GTINIT(CS_2_LOW_DECODE_ADDRESS, UNCACHED_TO_PHYS(UART_BASE) >> 20)
	GTINIT(CS_2_HIGH_DECODE_ADDRESS, (UNCACHED_TO_PHYS(UART_BASE) + UART_SIZE - 1) >> 20)

	GTINIT(CS_3_LOW_DECODE_ADDRESS, UNCACHED_TO_PHYS(FLASH_BASE) >> 20)
	GTINIT(CS_3_HIGH_DECODE_ADDRESS, (UNCACHED_TO_PHYS(FLASH_BASE) + FLASH_SIZE - 1) >> 20)

	/* end mark */
	.word	0, 0

1:
	sw	v1, 0(v0)
2:
	lw	v0, 0(ra)		/* Address */
	lw	v1, 4(ra)		/* Data */
	bnez	v0, 1b
	addiu	ra, 8


/*
 * BOOT rom. Read width bits to check boot width size to set up flash CS
 * "correctly". Bootwidth sticks with straps but for clarity we retain it
 * Also it should be correct to use the same timing for both flashes since
 * they can be swapped, although they may have different characteristics.
 */
	lw	t0, DEVICE_BOOT_BANK_PARAMETERS(s2)
	li	t1, HTOLE32(GT_DEVPAR_TurnOff(2) | GT_DEVPAR_AccToFirst(15) | \
			    GT_DEVPAR_AccToNext(15) | GT_DEVPAR_ALEtoWr(5) |  \
			    GT_DEVPAR_WrActive(7)   | GT_DEVPAR_WrHigh(5) |   \
			    GT_DEVPAR_Reserved)
	and	t0, HTOLE32(GT_DEVPAR_DevWidthMASK)
	or	t1, t0				/* DevWidth value */
	li	t2, HTOLE32(GT_DEVPAR_DevWidth32)
	beqz	t0, bootis32
	nop
//	sw	t1, DEVICE_BOOT_BANK_PARAMETERS(s2)

	li	t2, HTOLE32(GT_DEVPAR_DevWidth8)
bootis32:
	lw	t0, DEVICE_BANK3PARAMETERS(s2)		/* Flash Disk */
	and	t0, HTOLE32(GT_DEVPAR_ReservedMASK)
	or	t0, t2
	li	t1, HTOLE32(GT_DEVPAR_TurnOff(2) | GT_DEVPAR_AccToFirst(17) | \
			    GT_DEVPAR_AccToNext(17) | GT_DEVPAR_ALEtoWr(5) |  \
			    GT_DEVPAR_WrActive(7)   | GT_DEVPAR_WrHigh(7))
	or	t0, t1
	sw	t0, DEVICE_BANK3PARAMETERS(s2)

/*
 *  Init serial I/O for diagnostic output.
 */
	bal	initserial
	nop

	PRINTSTR("\r\nPMON2000 MIPS Initializing. Standby...\r\n")

	PRINTSTR("ERRORPC=")
	mfc0	a0, COP_0_ERROR_PC
	bal	hexserial
	nop

	PRINTSTR(" CONFIG=")
	mfc0	a0, COP_0_CONFIG
	bal	hexserial
	nop
	PRINTSTR("\r\n")

	la	s0, start		/* RA set from BAL above! */
	subu	s0, ra, s0		/* s0 is now load vs. link offset */
	and	s0, 0xffff0000		/* Mask off lower bits */


	TTYDBG("Setting up SDRAM controller\r\n");

 	/* Read the SPD info and get DRAM Configuration */	

	bal	doinit
	nop

	GTINIT(SCS_0_LOW_DECODE_ADDRESS,  0xfff)
	GTINIT(SCS_0_HIGH_DECODE_ADDRESS, 0x000)
	GTINIT(SCS_1_LOW_DECODE_ADDRESS,  0xfff)
	GTINIT(SCS_1_HIGH_DECODE_ADDRESS, 0x000)
	GTINIT(SCS_2_LOW_DECODE_ADDRESS,  0xfff)
	GTINIT(SCS_2_HIGH_DECODE_ADDRESS, 0x000)
	GTINIT(SCS_3_LOW_DECODE_ADDRESS,  0xfff)
	GTINIT(SCS_3_HIGH_DECODE_ADDRESS, 0x000)
#ifdef RUN_SDRAM_FAST
	GTINIT(SDRAM_TIMING_PARAMETERS, 0x0000072a)
#else
	GTINIT(SDRAM_TIMING_PARAMETERS, 0x0000072a)
#endif
	.word 0, 0

doinit:
	li	v0, 0xb0000000		/* ra is set from previous bal */
	bgtu	v0, ra, in_ram		/* if pc is lower than rom space.. */
	nop
	b	2f
	nop

1:
	sw	v1, 0(v0)
2:
	lw	v0, 0(ra)		/* Address */
	lw	v1, 4(ra)		/* Data */
	bnez	v0, 1b
	addiu	ra, 8

/*
 *  We are executing in ROM space so start do the setup work.
 *
 *  Initialize SDRAM. 
 *
 *  NOTE!!! We can't complete address mapping at this point
 *  because we cant't move the bootrom mapping until we are
 *  executing out of SDRAM. We start by setting both banks
 *  to 128MB and then once running from SDRAM we change the
 *  decoding to map the actual memory.
 */
#ifdef SKIPDIMM
	b	skipdimm
	nop
#endif
	bal	boot_i2c_init
	nop
	TTYDBG("Probing DIMM...\r\nDIMM0=");
	bal	probe_sdram_size
	li	a0, 0x600

	move	t2, v0
	bal	hexserial
	move	a0,v0

	TTYDBG("\r\nDIMM1=");
	
	bal	probe_sdram_size
	li	a0, 0x400
	
	move	t3, v0
	bal	hexserial
	move	a0, v0

	TTYDBG("\r\n");

	srl	s1, t2, 20

	add	t1, t2, t3
	beqz	t1, panic_no_memory
	nop

	bgt	t2, 256*1024*1024, panic_dimm0_too_big
	nop
	
	bnez		t2,	1f
	nop
	bgt	t3, 256*1024*1024, panic_dimm1_too_big
	nop
	b	sdram_slot1_config
	nop
1:
	bal	boot_i2c_read
	li	a0, 0x61f
	move t4, v0

	bal	boot_i2c_read
	li	a0, 0x604
	move	t5, v0

	bal	boot_i2c_read
	li	a0, 0x605
	beq	v0, 2, sdram_slot0_2bank
	nop
	
	TTYDBG("DIMM0: 1 side\r\n");
	
	li	t0, 0
	sw	t0, SCS_0_LOW_DECODE_ADDRESS(s2)
	srl	t0, t2, 20
	sub	t0, 1
	b sdram_slot1_config
	sw	t0, SCS_0_HIGH_DECODE_ADDRESS(s2)
	
sdram_slot0_2bank:
	TTYDBG("DIMM0: 2 sides\r\n");
	li	t0, 0
	sw	t0, SCS_0_LOW_DECODE_ADDRESS(s2)
	srl	t0, t2, 21
	sw	t0, SCS_1_LOW_DECODE_ADDRESS(s2)
	sub	t0, 1
	sw	t0, SCS_0_HIGH_DECODE_ADDRESS(s2)
	srl	t0, t2, 20
	sub	t0, 1
	sw	t0, SCS_1_HIGH_DECODE_ADDRESS(s2)
	
sdram_slot1_config:
	beqz	t3, sdram_set_param
	nop
	
	bal	boot_i2c_read
	li	a0, 0x41f
	move t6, v0

	bal	boot_i2c_read
	li	a0, 0x404
	move	t7, v0

	bal	boot_i2c_read
	li	a0, 0x405
	beq	v0, 2, sdram_slot1_2bank
	nop
	TTYDBG("DIMM1: 1 side\r\n");
	add	t1, t2, t3
	bgt	t1, 256*1024*1024, dimm1_set_high_1bank
	nop
	srl	t0, t2, 20
	sw	t0, SCS_2_LOW_DECODE_ADDRESS(s2)
	srl	t0, t1, 20
	sub	t0, 1
	sw	t0, SCS_2_HIGH_DECODE_ADDRESS(s2)
	srl	t0, t3, 20
	b sdram_set_param
	add	s1, s1, t0
dimm1_set_high_1bank:
	or	s1, s1, 0x80000000
	li	t0, 0x0200
	sw	t0, SCS_2_LOW_DECODE_ADDRESS(s2)
	addu	t0, t3, 0x20000000
	srl	t0, t0, 20
	sub	t0, 1
	sw	t0, SCS_2_HIGH_DECODE_ADDRESS(s2)
	srl	t0, t3, 4
	b	sdram_set_param
	or	s1, s1, t0
sdram_slot1_2bank:
	TTYDBG("DIMM1: 2 sides\r\n");

	bgt	t1, 256*1024*1024, dimm1_set_high_2bank
	nop

	srl	t0, t2, 20
	sw	t0, SCS_2_LOW_DECODE_ADDRESS(s2)
	srl	t0, t3, 1
	addu	t0, t0, t2
	srl	t0, t0, 20
	sw	t0, SCS_3_LOW_DECODE_ADDRESS(s2)
	sub	t0, 1
	sw	t0, SCS_2_HIGH_DECODE_ADDRESS(s2)
	addu	t0, t2, t3
	srl	t0, t0, 20
	sub	t0, 1
	sw	t0, SCS_3_HIGH_DECODE_ADDRESS(s2)
	srl	t0, t3, 20
	b	sdram_set_param
	add	s1, s1, t0
dimm1_set_high_2bank:
	or	s1, s1, 0x80000000
	li	t0, 0x0200
	sw	t0, SCS_2_LOW_DECODE_ADDRESS(s2)
	srl	t0, t3, 1
	addu	t0, t0, 0x20000000
	srl	t0, t0, 20
	sw	t0, SCS_3_LOW_DECODE_ADDRESS(s2)
	sub	t0, 1
	sw	t0, SCS_2_HIGH_DECODE_ADDRESS(s2)
	addu	t0, t3, 0x20000000
	srl	t0, t0, 20
	sub	t0, 1
	sw	t0, SCS_3_HIGH_DECODE_ADDRESS(s2)
	srl	t0, t3, 4
	or	s1, s1, t0
	
sdram_set_param:
	beqz	t2, skip_dimm0
	nop
	li	t0, HTOLE32(0x8000)
	li	v1, 0x10
	beq	t4, v1, set_dens0		/* 64MB */
	li	v1, 0x20
	beq	t4, v1, set_dens0		/* 128MB */
	li	v1, 0x40
	li	t0, HTOLE32(0xc000)
	beq	t4, v1, set_dens0		/* 256MB */
	li	v1, 0x80
	beq	t4, v1, set_dens0		/* 512MB */
	nop
	li	t0, HTOLE32(0x4000)
	li	v1, 10
	beq	t5, v1, set_dens0
	nop
	li	t0, HTOLE32(0x8000)
	b	set_dens0
	nop
skip_dimm0:
	beqz	t3, done_dens
	nop
	li	t0, HTOLE32(0x8000)
	li	v1, 0x10
	beq	t6, v1, set_dens1		/* 64MB */
	li	v1, 0x20
	beq	t6, v1, set_dens1		/* 128MB */
	li	v1, 0x40
	li	t0, HTOLE32(0xc000)
	beq	t6, v1, set_dens1		/* 256MB */
	li	v1, 0x80
	beq	t6, v1, set_dens1		/* 512MB */
	nop
	li	t0, HTOLE32(0x4000)
	li	v1, 10
	beq	t7, v1, set_dens1
	nop
	li	t0, HTOLE32(0x8000)
	b	set_dens1
	nop
set_dens0:
#ifdef RUN_SDRAM_FAST
	or	t0, 0x00f0000
#endif
	sw	t0, SDRAM_BANK0PARAMETERS(s2)
	sw	t0, SDRAM_BANK1PARAMETERS(s2)
	b	skip_dimm0
	nop
set_dens1:
#ifdef RUN_SDRAM_FAST
	or	t0, 0x00f0000
#endif
	sw	t0, SDRAM_BANK2PARAMETERS(s2)
	sw	t0, SDRAM_BANK3PARAMETERS(s2)
done_dens:
#ifdef RUN_SDRAM_FAST
	li	t0, HTOLE32(0x00e0c080)		/* non-registred */
#else
	li	t0, HTOLE32(0x04e0c080)		/* non-registred */
#endif
set_conf:
	sw	t0, SDRAM_CONFIGURATION(s2)

	li	t0, HTOLE32(2)
	sw	t0, SDRAM_ADDRESS_DECODE(s2)
	sw	zero, SDRAM_OPERATION_MODE(s2)
	b	2f
	nop
#ifdef SKIPDIMM
skipdimm:
	li	t0, 0x0000007f
	sw	t0, SCS_0_HIGH_DECODE_ADDRESS(s2)
	sw	zero, SCS_0_LOW_DECODE_ADDRESS(s2)
	li	t0, 0x000000ff
	sw	t0, SCS_1_HIGH_DECODE_ADDRESS(s2)
	li	t0, 0x00000080
	sw	t0, SCS_1_LOW_DECODE_ADDRESS(s2)

	li	t0, 0x00008000
	sw	t0, SDRAM_BANK0PARAMETERS(s2)
	sw	t0, SDRAM_BANK1PARAMETERS(s2)
	li	t0, HTOLE32(0x04e0c080)		/* non-registred */
	sw	t0, SDRAM_CONFIGURATION(s2)

#ifdef	SDRAM_MODE_FIX
	li	t0, HTOLE32(2)
	sw	t0, SDRAM_ADDRESS_DECODE(s2)
	/* MRS command issue */
	li	t0, HTOLE32(3)
	sw	t0, SDRAM_OPERATION_MODE(s2)
	lw	t0, SDRAM_OPERATION_MODE(s2)
	/* dummy write */
	li	t0, 0xa0000000
	sw	zero, 0(t0)
1:
	lw	t0, SDRAM_OPERATION_MODE(s2)
	and	t0, 0x80000000
	beqz	t0, 1b
	nop

	/* MRS command issue */
	li	t0, HTOLE32(3)
	sw	t0, SDRAM_OPERATION_MODE(s2)
	lw	t0, SDRAM_OPERATION_MODE(s2)
	/* dummy write */
	li	t0, 0xa0000000 + 1024*1024*128
	sw	zero, 0(t0)
1:
	lw	t0, SDRAM_OPERATION_MODE(s2)
	and	t0, 0x80000000
	beqz	t0, 1b
	nop
#endif
	sw	zero, SDRAM_OPERATION_MODE(s2)
	lw	t0, SDRAM_OPERATION_MODE(s2)
	
	b	2f
	nop
#endif	
panic_dimm0_too_big:
	PRINTSTR("\r\nPANIC! DIMM0 cannot exceed 256MB\r\n")
	b	1f
panic_dimm1_too_big:
	PRINTSTR("\r\nPANIC! DIMM1 cannot exceed 256MB if DIMM0 is absent\r\n")
	b	1f
panic_no_memory:
	PRINTSTR("\r\nPANIC! No SDRAM installed\r\n")
1:
	b	1b
	nop

2:

	TTYDBG("Dumping SDRAM registers...\r\n");
	
	
	TTYDBG("SDRAM_CONFIGURATION=");
	bal	hexserial
	lw	a0, SDRAM_CONFIGURATION(s2)

	TTYDBG("\r\nSDRAM_TIMING_PARAMETERS=");
	bal	hexserial
	lw	a0, SDRAM_TIMING_PARAMETERS(s2)

	TTYDBG("\r\nSDRAM_BANK0PARAMETERS=");
	bal	hexserial
	lw	a0, SDRAM_BANK0PARAMETERS(s2)

	TTYDBG("\r\nSDRAM_BANK1PARAMETERS=");
	bal	hexserial
	lw	a0, SDRAM_BANK1PARAMETERS(s2)

	TTYDBG("\r\nSDRAM_BANK2PARAMETERS=");
	bal	hexserial
	lw	a0, SDRAM_BANK2PARAMETERS(s2)
	
	TTYDBG("\r\nSDRAM_BANK3PARAMETERS=");
	bal	hexserial
	lw	a0, SDRAM_BANK3PARAMETERS(s2)
	
	TTYDBG("\r\nSCS_0=");
	bal	hexserial
	lw	a0, SCS_0_LOW_DECODE_ADDRESS(s2)
	TTYDBG("~");
	bal	hexserial
	lw	a0, SCS_0_HIGH_DECODE_ADDRESS(s2)

	TTYDBG("\r\nSCS_1=");
	bal	hexserial
	lw	a0, SCS_1_LOW_DECODE_ADDRESS(s2)
	TTYDBG("~");