pci_machdep.c

来自「国产CPU－龙芯（loongson)BIOS源代码」· C语言 代码 · 共 559 行 · 第 1/2 页

	 *  size register should be set to match SDRAM SCS.
         */
	
	_pci_conf_write(_pci_make_tag(0, 0, 0), PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, 0xf4000000);
	_pci_conf_write(_pci_make_tag(1, 0, 0), PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, 0xf4000000);
		
	for(i = 0; i < NBARS; i++) {
		u_int32_t baselo, basehi, enabler;
		pcitag_t tag;

		baselo = GT_READ(barlist[i].scslow);
		basehi = GT_READ(barlist[i].scshigh);
		if(baselo > basehi) { /* Disabled */
			baselo = 0;
			basehi = 0;
		}
		else {
			baselo = baselo << 20;
			basehi = (basehi << 20) | 0xfffff;
			printf("{%08x~%08x}\n", baselo, basehi);
		}
		
		tag = _pci_make_tag(0, 0, (barlist[i].bar0 & 0x700) >> 8);
		stat = _pci_conf_read(tag, barlist[i].bar0 & 0xff) & 0xffff;
		stat |= baselo & 0xfffff000;
		if (barlist[i].remap0 != 0)
			stat += PCI0_CPU_MEM_BASE;
		_pci_conf_write(tag, barlist[i].bar0 & 0xff, stat);
		tag = _pci_make_tag(1, 0, (barlist[i].bar0 & 0x700) >> 8);
		stat = _pci_conf_read(tag, barlist[i].bar0 & 0xff) & 0xffff;
		stat |= baselo & 0xfffff000;
		if (barlist[i].remap1 != 0)
			stat += PCI1_CPU_MEM_BASE;
		_pci_conf_write(tag, barlist[i].bar0 & 0xff, stat);
		GT_WRITE(barlist[i].pci0size, (basehi - baselo) & 0xfffff000);
		GT_WRITE(barlist[i].pci1size, (basehi - baselo) & 0xfffff000);
		if (barlist[i].remap0 != 0)
			GT_WRITE(barlist[i].remap0, 0x0);
		if (barlist[i].remap1 != 0)
			GT_WRITE(barlist[i].remap1, 0x0);
		if(!baselo && !basehi){
			enabler = GT_READ(PCI_0BASE_ADDRESS_REGISTERS_ENABLE);
			enabler |= barlist[i].enablemask;
			GT_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, enabler);
			GT_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, enabler);
		}
	}

	/*
         *  This target uses the internal arbiter
         */
        stat = GT_READ(PCI_0ARBITER_CONTROL);
        stat |= 0x80000000;
        GT_WRITE(PCI_0ARBITER_CONTROL, stat);
        stat = GT_READ(PCI_1ARBITER_CONTROL);
        stat |= 0x80000000;
        GT_WRITE(PCI_1ARBITER_CONTROL, stat); 

	return(2);
}


/*
 * Called to reinitialise the bridge after we've scanned each PCI device
 * and know what is possible. We also set up the interrupt controller
 * routing and level control registers.
 */
void
_pci_hwreinit (void)
{
}

void
_pci_flush (void)
{
}


/*
 *  Map the CPU virtual address of an area of local memory to a PCI
 *  address that can be used by a PCI bus master to access it.
 */
vm_offset_t
_pci_dmamap(va, len)
	vm_offset_t va;
	unsigned int len;
{
#if 0
	return(VA_TO_PA(va) + bus_dmamap_tag._dmamap_offs);
#endif
	return(pci_local_mem_pci_base + VA_TO_PA (va));
}

#if 0
/*
 *  Map the PCI address of an area of local memory to a CPU physical
 *  address.
 */
vm_offset_t
_pci_cpumap(pcia, len)
	vm_offset_t pcia;
	unsigned int len;
{
	return PA_TO_VA(pcia - pci_local_mem_pci_base);
}
#endif


/*
 *  Make pci tag from bus, device and function data.
 */
pcitag_t
_pci_make_tag(bus, device, function)
	int bus;
	int device;
	int function;
{
	pcitag_t tag;

	tag = (bus << 16) | (device << 11) | (function << 8);
	return(tag);
}

/*
 *  Break up a pci tag to bus, device function components.
 */
void
_pci_break_tag(tag, busp, devicep, functionp)
	pcitag_t tag;
	int *busp;
	int *devicep;
	int *functionp;
{
	if (busp) {
		*busp = (tag >> 16) & 255;
	}
	if (devicep) {
		*devicep = (tag >> 11) & 31;
	}
	if (functionp) {
		*functionp = (tag >> 8) & 7;
	}
}

int
_pci_canscan (pcitag_t tag)
{
	int bus, device, function;

	_pci_break_tag (tag, &bus, &device, &function); 
	if((bus == 0 || bus == 1) && device == 0) {
		return(0);		/* Ignore the Discovery itself */
	}
	return (1);
}

/*
 *  Read a value form PCI configuration space.
 */
pcireg_t
_pci_conf_readn(tag, reg, width)
	pcitag_t tag;
	int reg;
	int width;
{
	pcireg_t data;
	u_int32_t adr;
	int bus, device, function;
	if (reg & (width-1) || reg < 0 || reg >= 0x100) {
		if (_pciverbose >= 1) {
			_pci_tagprintf (tag, "_pci_conf_read: bad reg 0x%x\r\n", reg);
		}
		return ~0;
	}

	_pci_break_tag (tag, &bus, &device, &function); 
	/* Type 0 configuration on onboard PCI bus */
	if (device > 29 || function > 7) {
		return ~0;		/* device out of range */
	}
	adr = (device << 11) | (function << 8) | reg | GT_IPCI_CFGADDR_ConfigEn;
	if(bus == 0) {
		GT_WRITE(PCI_0CONFIGURATION_ADDRESS, adr);
		data = GT_READ(PCI_0CONFIGURATION_ADDRESS);
		if (data != adr)
			return 0xffffffff;
		if(width==4)
			data = GT_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER);
		else if(width==2)
			data = GT_READ_WORD(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER);
		else data = GT_READ_BYTE(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER);
	}
	else {
		GT_WRITE(PCI_1CONFIGURATION_ADDRESS, adr);
		data = GT_READ(PCI_1CONFIGURATION_ADDRESS);
		if (data != adr)
			return 0xffffffff;
		if(width==4)
			data = GT_READ(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER);
		else if(width==2)
			data = GT_READ_WORD(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER);
		else
			data = GT_READ_BYTE(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER);
			
	}
	return data;
}


pcireg_t
_pci_conf_read(pcitag_t tag, int reg)
{
	return _pci_conf_readn(tag, reg, 4);
}

/*
 *  Write a value to PCI configuration space.
 */
void
_pci_conf_writen(tag, reg, data, width)
	pcitag_t tag;
	int reg;
	pcireg_t data;
	int width;
{
	u_int32_t adr;
	int bus, device, function;

	if (reg & (width-1) || reg < 0 || reg >= 0x100) {
		if (_pciverbose >= 1) { 
			_pci_tagprintf(tag, "_pci_conf_write: bad reg 0x%x\r\n", reg);
		}
		return;
	}

	_pci_break_tag (tag, &bus, &device, &function);

	/* Type 0 configuration on onboard PCI buses */
	if (device > 29 || function > 7) {
		return;		/* device out of range */
	}
	adr = (device << 11) | (function << 8) | (reg & 0xfc) | GT_IPCI_CFGADDR_ConfigEn;

	if(bus == 0) {
		GT_WRITE(PCI_0CONFIGURATION_ADDRESS, adr);
		if(width==4)
			GT_WRITE(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, data);
		else if(width==2)
			GT_WRITE_WORD(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, (unsigned short)data);
		else GT_WRITE_BYTE(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, (unsigned char)data);
	}
	else {
		GT_WRITE(PCI_1CONFIGURATION_ADDRESS, adr);
		if(width==4)
			GT_WRITE(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER, data);
		else if(width==2)
			GT_WRITE_WORD(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER,(unsigned short)data);
		else GT_WRITE_WORD(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER, (unsigned char)data);
	}
}

void
_pci_conf_write(pcitag_t tag, int reg, pcireg_t data)
{
    _pci_conf_writen (tag, reg, data, 4);
}


void
pci_sync_cache(p, adr, size, rw)
	void *p;
	vm_offset_t adr;
	size_t size;
	int rw;
{
	CPU_IOFlushDCache(adr, size, rw);
}