it8172.h

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/*
 *      Board Level Definitions.
 */
#ifndef __BLX_EV8172_H__
#define __BLX_EV8172_H__

#ifdef __MIPSEB__
#define HTOLE32(v)      ((((v) & 0xff) << 24) | (((v) & 0xff00) << 8) | \
                                        (((v) >> 24) & 0xff) | (((v) >> 8) & 0xff00))
#else
#ifdef __MIPSEL__
#define HTOLE32(v)      (v)
#else
#error ENDIAN NOT DEFINED!
#endif
#endif

#define u32 unsigned int

#define NS16550HZ 1843200
#if !defined(USE_SUPERIO_UART)
#if BYTE_ORDER == LITTLE_ENDIAN
#define nsreg(x) unsigned char CAT(pad_,x)[3]; unsigned char x;
#define NSREG(x) ((x) * 4 + 3)
#endif
#if BYTE_ORDER == BIG_ENDIAN
#define nsreg(x) unsigned char x;unsigned char CAT(pad_,x)[3];
#define NSREG(x) ((x) * 4)
#endif
#else
#define nsreg(x)        unsigned char x;
#define NSREG(x)        (x)
#endif

#include "addrspace.h"

#define IT8172_BASE                     0x18000000
#define IT8172_PCI_IO_BASE              0x14000000
#define IT8172_PCI_MEM_BASE             0x0c000000
#define PCI_IO_SPACE          IT8172_PCI_IO_BASE      /* 0x14000000 */

/*
 * System registers offsets from IT8172_BASE
 */
#define IT_CMFPCR                       0x0
#define IT_DSRR                         0x2
#define IT_PCDCR                        0x4
#define IT_SPLLCR                       0x6
#define IT_CIDR                         0x10
#define IT_CRNR                         0x12
#define IT_CPUTR                        0x14
#define IT_CTCR                         0x16
#define IT_SDPR                         0xF0

/*
 * Power management register offset from IT8172_PCI_IO_BASE
 * Power Management Device Standby Register
 */
#define IT_PM_DSR                       0x15800

#define IT_PM_DSR_TMR0SB        0x0001
#define IT_PM_DSR_TMR1SB        0x0002
#define IT_PM_DSR_CIR0SB        0x0004
#define IT_PM_DSR_CIR1SB        0x0008
#define IT_PM_DSR_SCR0SB        0x0010
#define IT_PM_DSR_SCR1SB        0x0020
#define IT_PM_DSR_PPSB          0x0040
#define IT_PM_DSR_I2CSB         0x0080
#define IT_PM_DSR_UARTSB        0x0100
#define IT_PM_DSR_IDESB         0x0200
#define IT_PM_DSR_ACSB          0x0400
#define IT_PM_DSR_M68KSB        0x0800

/*
 *  Power Management PCI Device Software Reset Register
 */
#define IT_PM_PCISR             0x15802

#define IT_PM_PCISR_IDESR       0x0001
#define IT_PM_PCISR_CDMASR      0x0002
#define IT_PM_PCISR_USBSR       0x0004
#define IT_PM_PCISR_DMASR       0x0008
#define IT_PM_PCISR_ACSR        0x0010
#define IT_PM_PCISR_MEMSR       0x0020
#define IT_PM_PCISR_68KSR       0x0040


/*
 * PCI Configuration address and data register offsets
 * from IT8172_BASE
 */
#define IT_CONFADDR                             0x4000
#define IT_BUSNUM_SHF           16
#define IT_DEVNUM_SHF           11
#define IT_FUNCNUM_SHF          8
#define IT_REGNUM_SHF           2

#define IT_CONFDATA                             0x4004

/*
 * PCI configuration header common register offsets
 */
#define IT_VID                          0x00
#define IT_DID                          0x02
#define IT_PCICMD                       0x04
#define IT_PCISTS                       0x06
#define IT_RID                          0x08
#define IT_CLASSC                       0x09
#define IT_HEADT                        0x0E
#define IT_SERIRQC                      0x49

/*
 * PCI to Internal/LPC Bus Bridge configuration header register offset
 */
#define IT_P2I_BCR                                      0x4C
#define IT_P2I_D0IOSC                           0x50
#define IT_P2I_D1IOSC                           0x54
#define IT_P2I_D2IOSC                           0x58
#define IT_P2I_D3IOSC                           0x5C
#define IT_P2I_D4IOSC                           0x60
#define IT_P2I_D5IOSC                           0x64
#define IT_P2I_D6IOSC                           0x68
#define IT_P2I_D7IOSC                           0x6C
#define IT_P2I_D8IOSC                           0x70
#define IT_P2I_D9IOSC                           0x74
#define IT_P2I_D10IOSC                          0x78
#define IT_P2I_D11IOSC                          0x7C

/*
 *  Memory controller register offsets from IT8172_BASE
 */
#define IT_MC_SDRMR                                     0x1000
#define IT_MC_SDRTR                                     0x1004
#define IT_MC_MCR                                       0x1008
#define IT_MC_SDTYPE                            	0x100C
#define IT_MC_WPBA                                      0x1010
#define IT_MC_WPTA                                      0x1014
#define IT_MC_HATR                                      0x1018
#define IT_MC_PCICR                                     0x101C

/*
 * Flash/ROM control register offsets from IT8172_BASE
 */
#define IT_FC_BRCR                                      0x2000
#define IT_FC_FCR                                       0x2004
#define IT_FC_DCR                                       0x2008

/*
 * M68K interface bridge configuration header register offset
 */
#define IT_M68K_MBCSR                                   0x54
#define IT_M68K_TMR                                     0x58
#define IT_M68K_BCR                                     0x5C
#define IT_M68K_BSR                                     0x5D
#define IT_M68K_DTR                                     0x5F

/*
 * Register offset from IT8172_PCI_IO_BASE
 * These registers are accessible through 8172 PCI IO window.
 */

/*
 * INTC
 */
#define IT_INTC_BASE                            0x10000
#define IT_INTC_LBDNIRR                         0x10000
#define IT_INTC_LBDNIMR                         0x10002
#define IT_INTC_LBDNITR                         0x10004
#define IT_INTC_LBDNIAR                         0x10006
#define IT_INTC_LPCNIRR                         0x10010
#define IT_INTC_LPCNIMR                         0x10012
#define IT_INTC_LPCNITR                         0x10014
#define IT_INTC_LPCNIAR                         0x10016
#define IT_INTC_PDNIRR                          0x10020
#define IT_INTC_PDNIMR                          0x10022
#define IT_INTC_PDNITR                          0x10024
#define IT_INTC_PDNIAR                          0x10026
#define IT_INTC_UMNIRR                          0x10030
#define IT_INTC_UMNITR                          0x10034
#define IT_INTC_UMNIAR                          0x10036
#define IT_INTC_TYPER                           0x107FE

/*
 * IT8172 PCI device number
 */
#define IT_C2P_DEVICE                           0
#define IT_AUDIO_DEVICE                         1
#define IT_DMAC_DEVICE                          1
#define IT_CDMAC_DEVICE                         1
#define IT_USB_DEVICE                           1
#define IT_P2I_DEVICE                           1
#define IT_IDE_DEVICE                           1
#define IT_M68K_DEVICE                          1

/*
 * IT8172 PCI function number
 */
#define IT_C2P_FUNCION                          0
#define IT_AUDIO_FUNCTION                       0
#define IT_DMAC_FUNCTION                        1
#define IT_CDMAC_FUNCTION                       2
#define IT_USB_FUNCTION                         3
#define IT_P2I_FUNCTION                         4
#define IT_IDE_FUNCTION                         5
#define IT_M68K_FUNCTION                        6

/*
 * IT8172 GPIO
 */
#define IT_GPADR                                0x13800
#define IT_GPBDR                                0x13808
#define IT_GPCDR                                0x13810
#define IT_GPACR                                0x13802
#define IT_GPBCR                                0x1380A
#define IT_GPCCR                                0x13812
#define IT_GPAICR                               0x13804
#define IT_GPBICR                               0x1380C
#define IT_GPCICR                               0x13814
#define IT_GPAISR                               0x13806
#define IT_GPBISR                               0x1380E
#define IT_GPCISR                               0x13816
#define IT_GCR                                  0x13818

/*
 *  IT8172 RTC
 */
#define IT_RTC_BASE                             0x14800
#define IT_RTC_RIR0                             0x00
#define IT_RTC_RTR0                             0x01
#define IT_RTC_RIR1                             0x02
#define IT_RTC_RTR1                             0x03
#define IT_RTC_RIR2                             0x04
#define IT_RTC_RTR2                             0x05
#define IT_RTC_RCTR                             0x08
#define IT_RTC_RA                               0x0A
#define IT_RTC_RB                               0x0B
#define IT_RTC_RC                               0x0C
#define IT_RTC_RD                               0x0D

#define RTC_SEC_INDEX                           0x00
#define RTC_MIN_INDEX                           0x02
#define RTC_HOUR_INDEX                          0x04
#define RTC_DAY_INDEX                           0x06
#define RTC_DATE_INDEX                          0x07
#define RTC_MONTH_INDEX                         0x08
#define RTC_YEAR_INDEX                          0x09
#define RTC_REGA_INDEX                          0x0A
#define RTC_REGB_INDEX                          0x0B
#define RTC_REGC_INDEX                          0x0C
#define RTC_REGD_INDEX                          0x0D

#define RTC_NVRAM_BASE                          0x0e
#define RTC_INDEX_REG_BANK1                     0x02
#define RTC_DATA_REG_BANK1                      0x03

/*
 * IT8172 internal device registers
 */
#define IT_TIMER_BASE                           0x10800
#define IT_CIR0_BASE                            0x11000
#define IT_UART_BASE                            0x11800