mips.h

国产CPU－龙芯（loongson)BIOS源代码

#define SR_FR		0x04000000	/* Enable extra floating-point registers */
#define SR_SR		0x00100000	/* Soft Reset */
#define SR_CH		0x00040000	/* Cache Hit */
#define SR_CE		0x00020000	/* Cache ECC register modifies check bits */
#define SR_DE		0x00010000	/* Disable cache errors */

#define SR_KX		0x00000080	/* xtlb in kernel mode */
#define SR_SX		0x00000040	/* mips3 & xtlb in supervisor mode */
#define SR_UX		0x00000020	/* mips3 & xtlb in user mode */

#define SR_KSU_MASK	0x00000018	/* ksu mode mask */
#define SR_KSU_USER	0x00000010	/* user mode */
#define SR_KSU_SUPV	0x00000008	/* supervisor mode */
#define SR_KSU_KERN	0x00000000	/* kernel mode */

#define SR_ERL		0x00000004	/* error level */
#define SR_EXL		0x00000002	/* exception level */
#define SR_IE		0x00000001 	/* interrupt enable */
#endif /* R4000 */

#define SR_IMASK	0x0000ff00	/* Interrupt Mask */
#define SR_IMASK8	0x00000000	/* Interrupt Mask level=8 */
#define SR_IMASK7	0x00008000	/* Interrupt Mask level=7 */
#define SR_IMASK6	0x0000c000	/* Interrupt Mask level=6 */
#define SR_IMASK5	0x0000e000	/* Interrupt Mask level=5 */
#define SR_IMASK4	0x0000f000	/* Interrupt Mask level=4 */
#define SR_IMASK3	0x0000f800	/* Interrupt Mask level=3 */
#define SR_IMASK2	0x0000fc00	/* Interrupt Mask level=2 */
#define SR_IMASK1	0x0000fe00	/* Interrupt Mask level=1 */
#define SR_IMASK0	0x0000ff00	/* Interrupt Mask level=0 */

#define SR_IBIT8	0x00008000	/*  (Intr5) */
#define SR_IBIT7	0x00004000	/*  (Intr4) */
#define SR_IBIT6	0x00002000	/*  (Intr3) */
#define SR_IBIT5	0x00001000	/*  (Intr2) */
#define SR_IBIT4	0x00000800	/*  (Intr1) */
#define SR_IBIT3	0x00000400	/*  (Intr0) */
#define SR_IBIT2	0x00000200	/*  (Software Interrupt 1) */
#define SR_IBIT1	0x00000100	/*  (Software Interrupt 0) */

/* Cause Register */
#define CAUSE_BD		0x80000000	/* Branch Delay */
#define CAUSE_CEMASK		0x30000000	/* Coprocessor Error */
#define CAUSE_CESHIFT		28		/* Right justify CE  */
#define CAUSE_IPMASK		0x0000ff00	/* Interrupt Pending */
#define CAUSE_IPSHIFT		8		/* Right justify IP  */
#define CAUSE_IP8		0x00008000	/*  (Intr5) */
#define CAUSE_IP7		0x00004000	/*  (Intr4) */
#define CAUSE_IP6		0x00002000	/*  (Intr3) */
#define CAUSE_IP5		0x00001000	/*  (Intr2) */
#define CAUSE_IP4		0x00000800	/*  (Intr1) */
#define CAUSE_IP3		0x00000400	/*  (Intr0) */
#define CAUSE_SW2		0x00000200	/*  (Software Interrupt 1) */
#define CAUSE_SW1		0x00000100	/*  (Software Interrupt 0) */
#define CAUSE_EXCMASK		0x0000007c	/* Exception Code */
#define CAUSE_EXCSHIFT		2		/* Right justify EXC */

/* Exception Code */
/* XXX now defined in mips/cpu.h et al */
#define CEXC_INT	(0 << 2)	/* External interrupt */
#define CEXC_MOD	(1 << 2)	/* TLB modification */
#define CEXC_TLBL	(2 << 2)    	/* TLB miss (Load or Ifetch) */
#define CEXC_TLBS	(3 << 2)	/* TLB miss (Save) */
#define CEXC_ADEL	(4 << 2)    	/* Address error (Load or Ifetch) */
#define CEXC_ADES	(5 << 2)	/* Address error (Save) */
#define CEXC_IBE	(6 << 2)	/* Bus error (Ifetch) */
#define CEXC_DBE	(7 << 2)	/* Bus error (data load or store) */
#define CEXC_SYS	(8 << 2)	/* System call */
#define CEXC_BP		(9 << 2)	/* Break point */
#define CEXC_RI		(10 << 2)	/* Reserved instruction */
#define CEXC_CPU	(11 << 2)	/* Coprocessor unusable */
#define CEXC_OVF	(12 << 2)	/* Arithmetic overflow */
#ifdef R4000
#define CEXC_TRAP	(13 << 2)	/* Trap exception */
#define CEXC_VCEI	(14 << 2)	/* Virtual Coherency Exception (I) */
#define CEXC_FPE	(15 << 2)	/* Floating Point Exception */
#define CEXC_CP2	(16 << 2)	/* Cp2 Exception */
/*#define CEXC_C2E	(16 << 2)*/	/* Cp2 Exception */
#define CEXC_WATCH	(23 << 2)	/* Watchpoint exception */
#define CEXC_CACHE	(30 << 2)	/* Fake cache exception */
#define CEXC_VCED	(31 << 2)	/* Virtual Coherency Exception (D) */
#endif /* R4000 */

#ifdef R4000
#define	NTLBENTRIES	48
#else
#define	NTLBENTRIES	64
#endif

#define HI_HALF(x)	((x) >> 16)
#define LO_HALF(x)	((x) & 0xffff)

/* FPU stuff */
#define C1_CSR		$31
#define CSR_EMASK	(0x3f<<12)
#define CSR_TMASK	(0x1f<<7)
#define CSR_SMASK	(0x1f<<2)
#define C1_FRID		$0

#ifdef LR33020
#include "lr33020.h"
#endif

#ifdef R4000
/*
 * R4000 Config Register 
 */
#ifndef CFG_ECMASK
#define CFG_CM		0x80000000	/* Master-Checker mode */
#define CFG_ECMASK	0x70000000	/* System Clock Ratio */
#define CFG_ECSHIFT	28
#define CFG_ECBY2	0x00000000 	/* divide by 2 */
#define CFG_ECBY3	0x00000000 	/* divide by 3 */
#define CFG_ECBY4	0x00000000 	/* divide by 4 */
#define CFG_EPMASK	0x0f000000	/* Transmit data pattern */
#define CFG_EPD		0x00000000	/* D */
#define CFG_EPDDX	0x01000000	/* DDX */
#define CFG_EPDDXX	0x02000000	/* DDXX */
#define CFG_EPDXDX	0x03000000	/* DXDX */
#define CFG_EPDDXXX	0x04000000	/* DDXXX */
#define CFG_EPDDXXXX	0x05000000	/* DDXXXX */
#define CFG_EPDXXDXX	0x06000000	/* DXXDXX */
#define CFG_EPDDXXXXX	0x07000000	/* DDXXXXX */
#define CFG_EPDXXXDXXX	0x08000000	/* DXXXDXXX */
#define CFG_SBMASK	0x00c00000	/* Secondary cache block size */
#define CFG_SBSHIFT	22
#define CFG_SB4		0x00000000	/* 4 words */
#define CFG_SB8		0x00400000	/* 8 words */
#define CFG_SB16	0x00800000	/* 16 words */
#define CFG_SB32	0x00c00000	/* 32 words */
#define CFG_EMMASK	0x00c00000	/* Vr54xx: SysAD mode */
#define CFG_EMSHIFT	22
#define CFG_EM_R4K	0x00000000	/* Vr54xx: R4x000 compatible */
#define CFG_EM_SPLITRD	0x00400000	/* Vr54xx: Multiple split reads */
#define CFG_EM_PIPEWR	0x00800000	/* Vr54xx: Pipeline writes */
#define CFG_EM_WRREISSU	0x00c00000	/* Vr54xx: Write-reissue */
#define CFG_AD		0x00800000	/* Accelerated data (R4100) */
#define CFG_SS		0x00200000	/* Split secondary cache */
#define CFG_SW		0x00100000	/* Secondary cache port width */
#define CFG_EWMASK	0x000c0000	/* System port width */
#define CFG_EWSHIFT	18
#define CFG_EW64	0x00000000	/* 64 bit */
#define CFG_EW32	0x00040000	/* 32 bit */
#define CFG_SC		0x00020000	/* Secondary cache absent */
#define CFG_SM		0x00010000	/* Dirty Shared mode disabled */
#define CFG_BE		0x00008000	/* Big Endian */
#define CFG_EM		0x00004000	/* ECC mode enable */
#define CFG_EB		0x00002000	/* Block ordering */
#define CFG_ICMASK	0x00000e00	/* Instruction cache size */
#define CFG_ICSHIFT	9
#define CFG_DCMASK	0x000001c0	/* Data cache size */
#define CFG_DCSHIFT	6
#define CFG_IB		0x00000020	/* Instruction cache block size */
#define CFG_DB		0x00000010	/* Data cache block size */
#define CFG_CU		0x00000008	/* Update on Store Conditional */
#define CFG_K0MASK	0x00000007	/* KSEG0 coherency algorithm */
#endif CFG_ECMASK

/*
 * Primary cache mode
 */
#define CFG_C_WTHRU_NOALLOC	0	/* r4600 only */
#define CFG_C_WTHRU_ALLOC	1	/* r4600 only */
#define CFG_C_UNCACHED		2
#define CFG_C_NONCOHERENT	3
#define CFG_C_WBACK		3
#define CFG_C_COHERENTXCL	4
#define CFG_C_COHERENTXCLW	5 	
#define CFG_C_COHERENTUPD	6	/* r4000/r4400 only */
#define CFG_C_UNCACHED_ACCEL	7	/* t5 only */

/* 
 * Primary Cache TagLo 
 */
#define TAG_PTAG_MASK           0xffffff00      /* Primary Tag */
#define TAG_PTAG_SHIFT          8
#define TAG_PSTATE_MASK         0x000000c0      /* Primary Cache State */
#define TAG_PSTATE_SHIFT        6
#define TAG_PARITY_MASK         0x00000001      /* Primary Tag Parity */
#define TAG_PARITY_SHIFT        0

#define PSTATE_INVAL		0
#define PSTATE_SHARED		1
#define PSTATE_CLEAN_EXCL	2
#define PSTATE_DIRTY_EXCL	3

/* 
 * Secondary Cache TagLo 
 */
#ifndef TAG_STAG_MASK
#define TAG_STAG_MASK           0xffffe000      /* Secondary Tag */
#define TAG_STAG_SHIFT          13
#define TAG_SSTATE_MASK         0x00001c00      /* Secondary Cache State */
#define TAG_SSTATE_SHIFT        10
#define TAG_VINDEX_MASK         0x00000380      /* Secondary Virtual Index */
#define TAG_VINDEX_SHIFT        7
#define TAG_ECC_MASK            0x0000007f      /* Secondary Tag ECC */
#define TAG_ECC_SHIFT           0
#define TAG_STAG_SIZE		19		/* Secondary Tag Width */
#endif

#define SSTATE_INVAL		0
#define SSTATE_CLEAN_EXCL	4
#define SSTATE_DIRTY_EXCL	5
#define SSTATE_CLEAN_SHARED	6
#define SSTATE_DIRTY_SHARED	7

/*
 * R4000 CacheErr register
 */
#define CACHEERR_TYPE		0x80000000	/* reference type: 
						   0=Instr, 1=Data */
#define CACHEERR_LEVEL		0x40000000	/* cache level:
						   0=Primary, 1=Secondary */
#define CACHEERR_DATA		0x20000000	/* data field:
						   0=No error, 1=Error */
#define CACHEERR_TAG		0x10000000	/* tag field:
						   0=No error, 1=Error */
#define CACHEERR_REQ		0x08000000	/* request type:
						   0=Internal, 1=External */
#define CACHEERR_BUS		0x04000000	/* error on bus:
						   0=No, 1=Yes */
#define CACHEERR_BOTH		0x02000000	/* Data & Instruction error:
						   0=No, 1=Yes */
#define CACHEERR_REFILL		0x01000000	/* Error on Refill:
						   0=No, 1=Yes */
#define CACHEERR_SIDX_MASK	0x003ffff8	/* PADDR(21..3) */
#define CACHEERR_SIDX_SHIFT		 3
#define CACHEERR_PIDX_MASK	0x00000007	/* VADDR(14..12) */
#define CACHEERR_PIDX_SHIFT		12


/*
 * R4000 Cache operations
 */
#ifndef Index_Invalidate_I
#define Index_Invalidate_I               0x0         /* 0       0 */
#define Index_Writeback_Inv_D            0x1         /* 0       1 */
#define Index_Invalidate_SI              0x2         /* 0       2 */
#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
#define Index_Load_Tag_I                 0x4         /* 1       0 */
#define Index_Load_Tag_D                 0x5         /* 1       1 */
#define Index_Load_Tag_SI                0x6         /* 1       2 */
#define Index_Load_Tag_SD                0x7         /* 1       3 */
#define Index_Store_Tag_I                0x8         /* 2       0 */
#define Index_Store_Tag_D                0x9         /* 2       1 */
#define Index_Store_Tag_SI               0xA         /* 2       2 */
#define Index_Store_Tag_SD               0xB         /* 2       3 */
#define Create_Dirty_Exc_D               0xD         /* 3       1 */
#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
#define Hit_Invalidate_I                 0x10        /* 4       0 */
#define Hit_Invalidate_D                 0x11        /* 4       1 */
#define Hit_Invalidate_SI                0x12        /* 4       2 */
#define Hit_Invalidate_SD                0x13        /* 4       3 */
#define Fill_I                           0x14        /* 5       0 */
#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
#define Hit_Writeback_I                  0x18        /* 6       0 */
#define Hit_Writeback_D                  0x19        /* 6       1 */
#define Hit_Writeback_SD                 0x1B        /* 6       3 */
#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
#endif

/* Watchpoint Register */
#ifndef WATCH_PA
#define WATCH_PA	0xfffffff8
#define WATCH_R		0x00000002
#define WATCH_W		0x00000001
#endif

#define TLBMASK_MASKMASK	0x01ffe000
#define TLBMASK_MASK4Kb		0x00000000
#define TLBMASK_MASK16kb	0x00006000
#define TLBMASK_MASK64kb	0x0001e000
#define TLBMASK_MASK256kb	0x0007e000
#define TLBMASK_MASK1Mb		0x001fe000
#define TLBMASK_MASK4Mb		0x007fe000
#define TLBMASK_MASK16Mb	0x01ffe000

#define TLBMASK_4100_MASKMASK	0x0007f800
#define TLBMASK_4100_MASK1Kb	0x00000000
#define TLBMASK_4100_MASK4Kb	0x00001800
#define TLBMASK_4100_MASK16kb	0x00007800
#define TLBMASK_4100_MASK64kb	0x0001f800
#define TLBMASK_4100_MASK256kb	0x0007f800

/* FIXME 64bit TLB entries */
#define TLBHI_ASIDMASK		0x000000ff
#define TLBHI_VPN2MASK		0xffffe000
#define TLBHI_4100_VPN2MASK	0xfffff800

#define TLBLO_G			0x00000001
#define TLBLO_V			0x00000002
#define TLBLO_D			0x00000004
#define TLBLO_CALGMASK		0x00000038
#define TLBLO_PFNMASK		0x3fffffc0

#endif /* R4000 */

#define	PRID_PMC_RM5231A	(0x2831)
#define PRID_BLX_GODSONI	(0x4200)
#define PRID_BLX_GODSON2B	(0x6300)
#define PRID_BLX_GODSON2C	(0x6301)

#endif /* _MIPS_ */